From fb0d3acb140db6905bacbce92278feff0defa9f4 Mon Sep 17 00:00:00 2001
From: Michel Heily <michelheily@gmail.com>
Date: Fri, 5 Jul 2019 14:09:04 +0300
Subject: [PATCH] Impl Thumb Format 1 untested

Former-commit-id: e80617fd415ba951310a42c79b6ca37251d0e250
---
 src/arm7tdmi/arm/exec.rs   |  7 ++-----
 src/arm7tdmi/thumb/exec.rs | 19 ++++++++++++++++++-
 2 files changed, 20 insertions(+), 6 deletions(-)

diff --git a/src/arm7tdmi/arm/exec.rs b/src/arm7tdmi/arm/exec.rs
index 4a2b07d..811ebf2 100644
--- a/src/arm7tdmi/arm/exec.rs
+++ b/src/arm7tdmi/arm/exec.rs
@@ -91,7 +91,7 @@ impl Core {
         }
     }
 
-    fn register_shift(&mut self, reg: usize, shift: ArmRegisterShift) -> CpuResult<i32> {
+    pub fn register_shift(&mut self, reg: usize, shift: ArmRegisterShift) -> CpuResult<i32> {
         let val = self.get_reg(reg) as i32;
         match shift {
             ArmRegisterShift::ShiftAmount(amount, shift) => {
@@ -264,10 +264,8 @@ impl Core {
 
         if insn.load_flag() {
             let data = if insn.transfer_size() == 1 {
-                // +1N
                 self.load_8(addr, bus) as u32
             } else {
-                // +1N
                 self.load_32(addr, bus)
             };
 
@@ -275,7 +273,7 @@ impl Core {
 
             // +1I
             self.add_cycle();
-            // +y
+
             if insn.rd() == REG_PC {
                 pipeline_action = CpuPipelineAction::Flush;
             }
@@ -284,7 +282,6 @@ impl Core {
             if insn.transfer_size() == 1 {
                 self.store_8(addr, value as u8, bus);
             } else {
-                // +1N
                 self.store_32(addr, value, bus);
             };
         }
diff --git a/src/arm7tdmi/thumb/exec.rs b/src/arm7tdmi/thumb/exec.rs
index 3c1ee06..cfc0558 100644
--- a/src/arm7tdmi/thumb/exec.rs
+++ b/src/arm7tdmi/thumb/exec.rs
@@ -17,6 +17,22 @@ fn pop(cpu: &mut Core, bus: &mut Bus, r: usize) {
 }
 
 impl Core {
+    fn exec_thumb_move_shifted_reg(
+        &mut self,
+        bus: &mut Bus,
+        insn: ThumbInstruction,
+    ) -> CpuExecResult {
+        let result = self
+            .register_shift(
+                insn.rs(),
+                ArmRegisterShift::ShiftAmount(insn.offset5() as u8 as u32, insn.format1_op()),
+            )
+            .unwrap();
+        self.gpr[insn.rd()] = result as u32;
+
+        Ok(CpuPipelineAction::IncPC)
+    }
+
     fn exec_thumb_add_sub(&mut self, bus: &mut Bus, insn: ThumbInstruction) -> CpuExecResult {
         let op1 = self.get_reg(insn.rs()) as i32;
         let op2 = if insn.is_immediate_operand() {
@@ -222,6 +238,7 @@ impl Core {
 
     pub fn exec_thumb(&mut self, bus: &mut Bus, insn: ThumbInstruction) -> CpuExecResult {
         match insn.fmt {
+            ThumbFormat::MoveShiftedReg => self.exec_thumb_move_shifted_reg(bus, insn),
             ThumbFormat::AddSub => self.exec_thumb_add_sub(bus, insn),
             ThumbFormat::DataProcessImm => self.exec_thumb_data_process_imm(bus, insn),
             ThumbFormat::Mul => self.exec_thumb_mul(bus, insn),
@@ -233,7 +250,7 @@ impl Core {
             ThumbFormat::AddSp => self.exec_thumb_add_sp(bus, insn),
             ThumbFormat::PushPop => self.exec_thumb_push_pop(bus, insn),
             ThumbFormat::BranchConditional => self.exec_thumb_branch_with_cond(bus, insn),
-            _ => unimplemented!("thumb not implemented {:#?}", insn),
+            _ => unimplemented!("thumb not implemented {:#x?}", insn),
         }
     }
 }