diff --git a/src/arm7tdmi/arm/display.rs b/src/arm7tdmi/arm/display.rs
index aee3d1c..3b45c19 100644
--- a/src/arm7tdmi/arm/display.rs
+++ b/src/arm7tdmi/arm/display.rs
@@ -9,21 +9,21 @@ impl fmt::Display for ArmCond {
     fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
         use ArmCond::*;
         match self {
-            Equal => write!(f, "eq"),
-            NotEqual => write!(f, "ne"),
-            UnsignedHigherOrSame => write!(f, "cs"),
-            UnsignedLower => write!(f, "cc"),
-            Negative => write!(f, "mi"),
-            PositiveOrZero => write!(f, "pl"),
-            Overflow => write!(f, "vs"),
-            NoOverflow => write!(f, "vc"),
-            UnsignedHigher => write!(f, "hi"),
-            UnsignedLowerOrSame => write!(f, "ls"),
-            GreaterOrEqual => write!(f, "ge"),
-            LessThan => write!(f, "lt"),
-            GreaterThan => write!(f, "gt"),
-            LessThanOrEqual => write!(f, "le"),
-            Always => write!(f, ""), // the dissasembly should ignore this
+            EQ => write!(f, "eq"),
+            NE => write!(f, "ne"),
+            HS => write!(f, "cs"),
+            LO => write!(f, "cc"),
+            MI => write!(f, "mi"),
+            PL => write!(f, "pl"),
+            VS => write!(f, "vs"),
+            VC => write!(f, "vc"),
+            HI => write!(f, "hi"),
+            LS => write!(f, "ls"),
+            GE => write!(f, "ge"),
+            LT => write!(f, "lt"),
+            GT => write!(f, "gt"),
+            LE => write!(f, "le"),
+            AL => write!(f, ""), // the dissasembly should ignore this
         }
     }
 }
diff --git a/src/arm7tdmi/arm/mod.rs b/src/arm7tdmi/arm/mod.rs
index e5c0434..c226898 100644
--- a/src/arm7tdmi/arm/mod.rs
+++ b/src/arm7tdmi/arm/mod.rs
@@ -40,21 +40,21 @@ impl ArmDecodeError {
 
 #[derive(Debug, Copy, Clone, PartialEq, Primitive)]
 pub enum ArmCond {
-    Equal = 0b0000,
-    NotEqual = 0b0001,
-    UnsignedHigherOrSame = 0b0010,
-    UnsignedLower = 0b0011,
-    Negative = 0b0100,
-    PositiveOrZero = 0b0101,
-    Overflow = 0b0110,
-    NoOverflow = 0b0111,
-    UnsignedHigher = 0b1000,
-    UnsignedLowerOrSame = 0b1001,
-    GreaterOrEqual = 0b1010,
-    LessThan = 0b1011,
-    GreaterThan = 0b1100,
-    LessThanOrEqual = 0b1101,
-    Always = 0b1110,
+    EQ = 0b0000,
+    NE = 0b0001,
+    HS = 0b0010,
+    LO = 0b0011,
+    MI = 0b0100,
+    PL = 0b0101,
+    VS = 0b0110,
+    VC = 0b0111,
+    HI = 0b1000,
+    LS = 0b1001,
+    GE = 0b1010,
+    LT = 0b1011,
+    GT = 0b1100,
+    LE = 0b1101,
+    AL = 0b1110,
 }
 
 #[derive(Debug, Copy, Clone, PartialEq)]
@@ -438,7 +438,7 @@ mod tests {
         // ldreq r2, [r5, -r6, lsl #5]
         let decoded = ArmInstruction::decode(0x07_15_22_86, 0).unwrap();
         assert_eq!(decoded.fmt, ArmFormat::LDR_STR);
-        assert_eq!(decoded.cond, ArmCond::Equal);
+        assert_eq!(decoded.cond, ArmCond::EQ);
         assert_eq!(decoded.load_flag(), true);
         assert_eq!(decoded.pre_index_flag(), true);
         assert_eq!(decoded.write_back_flag(), false);
@@ -482,7 +482,7 @@ mod tests {
         // strteq r2, [r4], -r7, asr #8
         let decoded = ArmInstruction::decode(0x06_24_24_47, 0).unwrap();
         assert_eq!(decoded.fmt, ArmFormat::LDR_STR);
-        assert_eq!(decoded.cond, ArmCond::Equal);
+        assert_eq!(decoded.cond, ArmCond::EQ);
         assert_eq!(decoded.load_flag(), false);
         assert_eq!(decoded.pre_index_flag(), false);
         assert_eq!(decoded.write_back_flag(), true);
@@ -526,7 +526,7 @@ mod tests {
         // str r4, [sp, 0x10]
         let decoded = ArmInstruction::decode(0xe58d4010, 0).unwrap();
         assert_eq!(decoded.fmt, ArmFormat::LDR_STR);
-        assert_eq!(decoded.cond, ArmCond::Always);
+        assert_eq!(decoded.cond, ArmCond::AL);
 
         let mut core = Core::new();
         core.set_reg(4, 0x12345678);
diff --git a/src/arm7tdmi/cpu.rs b/src/arm7tdmi/cpu.rs
index 6d46620..dba97cc 100644
--- a/src/arm7tdmi/cpu.rs
+++ b/src/arm7tdmi/cpu.rs
@@ -256,21 +256,21 @@ impl Core {
     pub fn check_arm_cond(&self, cond: ArmCond) -> bool {
         use ArmCond::*;
         match cond {
-            Equal => self.cpsr.Z(),
-            NotEqual => !self.cpsr.Z(),
-            UnsignedHigherOrSame => self.cpsr.C(),
-            UnsignedLower => !self.cpsr.C(),
-            Negative => self.cpsr.N(),
-            PositiveOrZero => !self.cpsr.N(),
-            Overflow => self.cpsr.V(),
-            NoOverflow => !self.cpsr.V(),
-            UnsignedHigher => self.cpsr.C() && !self.cpsr.Z(),
-            UnsignedLowerOrSame => !self.cpsr.C() && self.cpsr.Z(),
-            GreaterOrEqual => self.cpsr.N() == self.cpsr.V(),
-            LessThan => self.cpsr.N() != self.cpsr.V(),
-            GreaterThan => !self.cpsr.Z() && (self.cpsr.N() == self.cpsr.V()),
-            LessThanOrEqual => self.cpsr.Z() || (self.cpsr.N() != self.cpsr.V()),
-            Always => true,
+            EQ => self.cpsr.Z(),
+            NE => !self.cpsr.Z(),
+            HS => self.cpsr.C(),
+            LO => !self.cpsr.C(),
+            MI => self.cpsr.N(),
+            PL => !self.cpsr.N(),
+            VS => self.cpsr.V(),
+            VC => !self.cpsr.V(),
+            HI => self.cpsr.C() && !self.cpsr.Z(),
+            LS => !self.cpsr.C() || self.cpsr.Z(),
+            GE => self.cpsr.N() == self.cpsr.V(),
+            LT => self.cpsr.N() != self.cpsr.V(),
+            GT => !self.cpsr.Z() && (self.cpsr.N() == self.cpsr.V()),
+            LE => self.cpsr.Z() || (self.cpsr.N() != self.cpsr.V()),
+            AL => true,
         }
     }