From fe9feb3498e46456efbf7c590f19299cbf4e2583 Mon Sep 17 00:00:00 2001
From: Tibor Nagy <xnagytibor@gmail.com>
Date: Thu, 14 May 2020 14:04:09 +0200
Subject: [PATCH] core: Handle lsr 32 correctly Shifter tests from the mGBA
 test suite now pass with a 140/140 score. Also fixes
 gba::tests::test_arm7tdmi_thumb_eggvance.

Former-commit-id: 4cd4faa3b33f04969b38480c5eed8bf352be025a
Former-commit-id: d1427d8c9b407be1505c0153cce1ecdadd646664
---
 rustboyadvance-core/src/arm7tdmi/alu.rs | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/rustboyadvance-core/src/arm7tdmi/alu.rs b/rustboyadvance-core/src/arm7tdmi/alu.rs
index def9cc9..e31414f 100644
--- a/rustboyadvance-core/src/arm7tdmi/alu.rs
+++ b/rustboyadvance-core/src/arm7tdmi/alu.rs
@@ -138,6 +138,10 @@ impl Core {
                     self.bs_carry_out = (val >> (amount - 1) & 1) == 1;
                     val >> amount
                 }
+                32 => {
+                    self.bs_carry_out = val.bit(31);
+                    0
+                }
                 _ => {
                     self.bs_carry_out = false;
                     0