Michel Heily
7119ba2451
Cpu: Rewrite pipeline code.
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Pipeline code was unreadable up until now, this also fixes a bug:
* Some roms have illegal instructions right after branch instructions, and
the cpu would error trying to decode them because of pipelining.
Former-commit-id: e3201c7b0d2adfc772231a3e2d5909f43c17b50f
2019-07-20 16:03:37 +03:00
Michel Heily
1f074e20ad
Refactor lcd -> gpu
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Former-commit-id: c12be139770922bac55490c76348f5406fc00f07
2019-07-16 01:21:11 +03:00
Michel Heily
c92bde54a1
Begin modeling DMA
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Former-commit-id: 83ab601e70666f76ed3ebfb22340c6b1868af3ac
2019-07-07 01:47:51 +03:00
Michel Heily
3cc84b1b03
Model many things
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Former-commit-id: b87fa2b16b395f497cf217ea043e68404ab2f65e
2019-07-06 15:54:07 +03:00
Michel Heily
58e1230e7a
Model the cartidge.
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Former-commit-id: b51d2928631bfc438b9f1b15fafcaa9d90008179
2019-07-03 01:40:08 +03:00
Michel Heily
6f81c236a6
Mega Commit #2 - Add some thumb decoding and disassembly
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Former-commit-id: e3a89ac681a8d6f6f0bee85b32f64d181e11242f
2019-07-03 00:03:35 +03:00
Michel Heily
cbddeffd91
arm: Implement MSR_REG and fix some prefetching errors
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Former-commit-id: 177b8966159ed86472b0d4d031363df72d46807a
2019-07-02 16:53:29 +03:00
Michel Heily
22c175d9cc
Reorganize package structure
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Former-commit-id: d7ad26c07fc7063522fae061577f7ceece797ae5
2019-07-01 16:15:42 +03:00
