Michel Heily
|
967ccca8dd
|
Mega commit - model CPU pipelining.
I except many bugs to arise..
Former-commit-id: bcc6ea57af803f783b0dd548b50956b3ccda2b1a
|
2019-06-29 22:23:12 +03:00 |
|
|
Michel Heily
|
fc6410b510
|
debugger: Make prompt bold
|
2019-06-27 15:04:15 +03:00 |
|
|
Michel Heily
|
b9d1d38c2d
|
debugger: Few improvements
|
2019-06-27 13:16:00 +03:00 |
|
|
Michel Heily
|
8a057ba159
|
debugger: Remember last command
|
2019-06-27 13:15:46 +03:00 |
|
|
Michel Heily
|
587ec3fc91
|
debugger: Add history to repl
|
2019-06-27 13:15:46 +03:00 |
|
|
Michel Heily
|
f45a856835
|
Support assignment expressions for registers!
|
2019-06-27 13:15:46 +03:00 |
|
|
Michel Heily
|
f1f33d8586
|
Improve debugger repl parsing.
Add assignment expressions, add tests, and cleanup code.
|
2019-06-27 13:15:46 +03:00 |
|
|
Michel Heily
|
fc400ace5f
|
Improve debug repl parsing :)
|
2019-06-27 13:15:46 +03:00 |
|