Michel Heily
53115a9a58
Refactor core functionality into a separate module
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Former-commit-id: 5d55b9eb0b63ed7c61465b4e814782165caa5002
2019-07-20 16:46:00 +03:00
Michel Heily
7119ba2451
Cpu: Rewrite pipeline code.
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Pipeline code was unreadable up until now, this also fixes a bug:
* Some roms have illegal instructions right after branch instructions, and
the cpu would error trying to decode them because of pipelining.
Former-commit-id: e3201c7b0d2adfc772231a3e2d5909f43c17b50f
2019-07-20 16:03:37 +03:00
Michel Heily
1f074e20ad
Refactor lcd -> gpu
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Former-commit-id: c12be139770922bac55490c76348f5406fc00f07
2019-07-16 01:21:11 +03:00
Michel Heily
1084be52b8
WIP mode0 rendering
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Former-commit-id: 6bce375f9373bbddf4522da5ecc2ea3584373847
2019-07-15 19:23:16 +03:00
Michel Heily
1747addcd3
Start modeling the Lcd Display
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Former-commit-id: 544f185c6f9eead870032170292b1cc8afc724bf
2019-07-11 18:17:28 +03:00
Michel Heily
c92bde54a1
Begin modeling DMA
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Former-commit-id: 83ab601e70666f76ed3ebfb22340c6b1868af3ac
2019-07-07 01:47:51 +03:00
Michel Heily
3cc84b1b03
Model many things
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Former-commit-id: b87fa2b16b395f497cf217ea043e68404ab2f65e
2019-07-06 15:54:07 +03:00
