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Author SHA1 Message Date
Michel Heily e06c77b6fd armwrestler-fix: Fix MULL_MLAL instructions 
Also fix disassembly for MULL_MLAL


Former-commit-id: f535b2db7edb5d056160699436dbeb0c15e61388
 2019-07-27 18:57:20 +03:00
Michel Heily 7429236471 Fix mistake in UMLAL 
Former-commit-id: 6fe9bdf5471b71b58dcf9ee9ffa03c41b24e6301
 2019-07-26 17:55:50 +03:00
Michel Heily 1b5626a1a7 armwrestler-fix: Refactor barrel shifter and fix ALU carry flag, hopefully for good. 
Passing most of armwrestler ALU tests (still have bugs in UMULL and
SMULL)


Former-commit-id: 3c57ca9b5360b5c9bba74b00a5bede5a8cc496af
 2019-07-26 17:55:50 +03:00
Michel Heily 24483456ed armwrestler-fix: Fix writeback for LDR where rd==rn 
Instead of returning an Err, the writeback should just be disabled.


Former-commit-id: 91636a4eeaf76d0dbd11d250202671fcf8aaa4e6
 2019-07-22 20:33:31 +03:00
Michel Heily 009e46f6d5 armwrestler-fix: Properly handle misaligned addresses LDR/LDRH/LDRSH 
Former-commit-id: 742a7c2b8413fa9d45df1575a0b14b8d1ab697c4
 2019-07-22 20:25:40 +03:00
Michel Heily 2a66e525b1 Fix thumb disassembly of LDMIA/STMIA 
Former-commit-id: b04b07f181fff82869503671dd0f500a6c3e5fb1
 2019-07-22 09:31:35 +03:00
Michel Heily 2fb6f3c884 Implement (psr / usr bank) transfers for LDM_STM 
Former-commit-id: 140e6a6c75f65f08f645b1a0ff2ca7c065438ce4
 2019-07-22 09:21:49 +03:00
Michel Heily 0b5902c52e Implement special MRS 
Former-commit-id: 1af358887ef71344987f72d65612095c72565f43
 2019-07-22 09:21:45 +03:00
Michel Heily c0d437b1a1 Fix exceptions and dataprocess mode change 
Former-commit-id: 5892131496904b621398212b9dfc077242fa9557
 2019-07-22 01:16:48 +03:00
Michel Heily 7501adfd12 Implement thumb17 (Swi) 
Former-commit-id: 62d7e14e9b84e74d9236e1f0a5e961ae805f861c
 2019-07-22 01:15:58 +03:00
Michel Heily eea26d2393 thumb: Change ordering when decoding thumb instruction. 
This fixes a bug where "swi" instructions are decoded as conditional
branches.

The order really matters here, because Swi instructions are actually
conditional branch with illegal condition code.


Former-commit-id: 0024a8b53386a510dd321c157391c99a2af29223
 2019-07-22 00:25:26 +03:00
Michel Heily 387e26fad9 Add support for BGMode3 (tonc first.gba example now working) 
Former-commit-id: 52ac773ee2c3542ff3b046c3ea33fde02e804492
 2019-07-22 00:09:44 +03:00
Michel Heily 7e9c0e31da Add minifb backend - Armwrestler now plays ! 
Former-commit-id: d72ea9139e04624322cf3bc4a8ab330f6bb133a4
 2019-07-20 23:02:18 +03:00
Michel Heily 61e1f055f1 Model the keypad 
Former-commit-id: 4f38fa754e3ee809a7386351297decb2d7f1451f
 2019-07-20 22:58:29 +03:00
Michel Heily 53115a9a58 Refactor core functionality into a separate module 
Former-commit-id: 5d55b9eb0b63ed7c61465b4e814782165caa5002
 2019-07-20 16:46:00 +03:00
Michel Heily 0f73abaf98 Optimize instructions with "register lists" (LDM_STM) 
These instruction (probably) allocated a vector each time.


Former-commit-id: 66f724e21e1e5d667d19c1f21d2cc4fa3944faac
 2019-07-20 16:07:19 +03:00
Michel Heily 7119ba2451 Cpu: Rewrite pipeline code. 
Pipeline code was unreadable up until now, this also fixes a bug:

* Some roms have illegal instructions right after branch instructions, and
the cpu would error trying to decode them because of pipelining.


Former-commit-id: e3201c7b0d2adfc772231a3e2d5909f43c17b50f
 2019-07-20 16:03:37 +03:00
Michel Heily 1f074e20ad Refactor lcd -> gpu 
Former-commit-id: c12be139770922bac55490c76348f5406fc00f07
 2019-07-16 01:21:11 +03:00
Michel Heily 876cdfdcb3 Implement MODE4 rendering, ArmWrestler renders now! 
Former-commit-id: 4910a63b454ae9309abc0aa584a7d0bc96143538
 2019-07-15 20:49:47 +03:00
Michel Heily 1084be52b8 WIP mode0 rendering 
Former-commit-id: 6bce375f9373bbddf4522da5ecc2ea3584373847
 2019-07-15 19:23:16 +03:00
Michel Heily 9d8272b895 Fix wrong use of rust ranges in the lcd.rs module 
Former-commit-id: 73d588299baed7f5206b904f40ecf4a4e5283ef6
 2019-07-15 19:09:41 +03:00
Michel Heily a4925b7233 Fix SP values for "--skip-bios" 
Former-commit-id: d89d3c9c6b5d062137442df4017d59dea047270f
 2019-07-15 07:31:29 +03:00
Michel Heily 0500d33cb7 Refactor bus interface 
Former-commit-id: f325cda23f5e9946b367456d82ba71bb92bdd46e
 2019-07-15 07:30:52 +03:00
Michel Heily f08da850c7 thumb: Fix overflowing multiplication 
Former-commit-id: 5dbd45f9fd3811726aad9c32444f0dcf42d0b8be
 2019-07-13 23:33:37 +03:00
Michel Heily ab8c067616 Flush pipelines when entering an exception 
Former-commit-id: c00754b8156ecac66cc0a72f6a7c73ee700448f0
 2019-07-13 23:33:10 +03:00
Michel Heily fb5229705b Refactor and fix arm condition check 
Former-commit-id: 132c14fc56a21426263971e2d544ff10f072fea1
 2019-07-13 23:32:43 +03:00
Michel Heily 1747addcd3 Start modeling the Lcd Display 
Former-commit-id: 544f185c6f9eead870032170292b1cc8afc724bf
 2019-07-11 18:17:28 +03:00
Michel Heily 95f45e55a9 arm: Impl MULL_MLAL and fix writeback for post-index memory transfers 
Also some minor fixes and formatting


Former-commit-id: 4929b28cbb4eeeed5acfbdcdd19392ffa3bb0f37
 2019-07-11 18:10:58 +03:00
Michel Heily 4763f79abf arm: Impl MLA 
Former-commit-id: fe2c836bd09af165381537445dd288ca7bac24ce
 2019-07-11 00:02:39 +03:00
Michel Heily 5bc4c79d6e arm: Implement MRS 
Former-commit-id: 8c1528b2bcd08096f929c4ee940f1a1f5eac2911
 2019-07-10 23:54:45 +03:00
Michel Heily 5f625b2209 Add special case for MSR immediate 
Former-commit-id: f9fabb3c0d7c05243866b712096c2c82cf41672d
 2019-07-10 23:48:14 +03:00
Michel Heily a9bf2d25e0 arm: Implement Arm MSR_FLAGS 
Former-commit-id: 64d2cf255304ecca02dadc55266d22bc1f92bb4c
 2019-07-10 22:35:40 +03:00
Michel Heily 4c3379615a Fix bug in RRX (defined "old_carry" after changing it >< ) 
Former-commit-id: b890d40bb57da1cc6b63d6436bc8f346131fa5bc
 2019-07-10 22:35:40 +03:00
Michel Heily 50086a8715 Fix word alignment for arm BX 
Former-commit-id: 9223259793cd8ecccb02b40c428d32315c632bff
 2019-07-10 22:35:40 +03:00
Michel Heily 2864f83681 Arm: Partially implement MUL 
Former-commit-id: 3b37f5cbe327e15be4cee56572c2230dbda48082
 2019-07-10 22:35:40 +03:00
Tamir 543161d6b8 Fix cli help lines to all follow the same structure 
Help lines all start with a capital letter and don't end with a dot


Former-commit-id: 31e65514d15540538e2de528810957e16c8b5090
 2019-07-10 12:59:48 +03:00
Michel Heily 92f65794d8 Fix writeback for Thumb LdmStm 
Former-commit-id: 00a15dc99716290da7b260b261090454d621ce8a
 2019-07-09 02:20:32 +03:00
Michel Heily 65de0c4e9d Thumb 4 - Take care of "neg" case. 
I overlooked it :/


Former-commit-id: 360eb755bcf343cddd98807e9faeff007c94cf64
 2019-07-09 01:30:24 +03:00
Michel Heily 34233fa654 alu: Fix bug in SBC and RSC ops 
Former-commit-id: 1cb23d6280e1816395c46a7571dd9f48df870202
 2019-07-09 01:29:34 +03:00
Michel Heily 19e4196384 Thumb 4 - Set flags if needed (For CMP) 
Former-commit-id: 4f5bc97375c8aa45036b025a3420331a8137da17
 2019-07-09 01:28:14 +03:00
Michel Heily 0bdf4993ee thumb: Word align PC when jumping to Arm code 
Former-commit-id: 55fa28246c45a6bd807c53ce8bf0bb5865d36564
 2019-07-09 01:27:23 +03:00
Michel Heily 6ddb136852 alu: Also fix carry detection for unsigned addition 
Former-commit-id: d405f885e2b54c23aef5faab86cc1da681bd05ec
 2019-07-09 00:40:52 +03:00
Michel Heily 6c0df33597 Finally got the barrel shifter right? 
The barrel shifter sure has lots of edge cases, need to implement tests ASAP


Former-commit-id: 989fc4477f610603154404d0ed4335619ebd6345
 2019-07-09 00:33:53 +03:00
Michel Heily 2817db4e1c alu: Fix carry detection for subtraction 
Former-commit-id: c9d8612f72ce4a002ea33446209bd7e6da0eb5aa
 2019-07-09 00:33:53 +03:00
Michel Heily 1bacb927af Fix ROR with amount > 32 
Former-commit-id: 8f88de3c55c0e452266c40944ff920175b83627e
 2019-07-08 21:03:47 +03:00
Michel Heily 9421281381 Fix THUMB 1 
I didn't send this through the ALU :/


Former-commit-id: 40b4d23dcd769496e9dcd47bbf8d472b91e6a7bf
 2019-07-08 20:58:22 +03:00
Michel Heily f7b2b48e5d Refactor ALU code into its own module, and fix things. 
* Fix overflow flag being ignored
* Fix barrel shifter misimplementations
* Rustfmt fixes


Former-commit-id: a14d50372f7850a04b204accf4e5d8b924e4b48e
 2019-07-08 20:57:58 +03:00
Michel Heily ecdd6e0ed4 thumb: Fix ALU ops for barrel shifter opcodes 
I kinda missed these when I read the manual ><


Former-commit-id: 7d6c21b6c3b46bf065a177c1c7f7a7a1baa6b8fa
 2019-07-08 01:47:41 +03:00
Michel Heily 163d8bda59 Fix not flushing the pipeline for "mov pc, reg" instructions 
Former-commit-id: 66136ef70b8f48d5e9f4c10b65f1e2fbd3dd3ea1
 2019-07-08 00:58:09 +03:00
Michel Heily 863838a4a4 Force R15 alignment via cpu.set_reg 
I've encounted many bugs with instructions that write PC but don't align
it.


Former-commit-id: b6a234564729f83c0b5e8adfa293227299aad4ac
 2019-07-08 00:57:18 +03:00