Michel Heily
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7e9c0e31da
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Add minifb backend - Armwrestler now plays !
Former-commit-id: d72ea9139e04624322cf3bc4a8ab330f6bb133a4
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2019-07-20 23:02:18 +03:00 |
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Michel Heily
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1084be52b8
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WIP mode0 rendering
Former-commit-id: 6bce375f9373bbddf4522da5ecc2ea3584373847
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2019-07-15 19:23:16 +03:00 |
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Michel Heily
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efb5d361d6
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Add PaletteView command for the debugger.
Former-commit-id: c4e0250eea700cfbcbb9f904cde7b6bc055d3e05
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2019-07-06 16:04:43 +03:00 |
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Michel Heily
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cbddeffd91
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arm: Implement MSR_REG and fix some prefetching errors
Former-commit-id: 177b8966159ed86472b0d4d031363df72d46807a
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2019-07-02 16:53:29 +03:00 |
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Michel Heily
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967ccca8dd
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Mega commit - model CPU pipelining.
I except many bugs to arise..
Former-commit-id: bcc6ea57af803f783b0dd548b50956b3ccda2b1a
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2019-06-29 22:23:12 +03:00 |
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Michel Heily
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a70b92d5a4
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Rename project
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2019-06-27 13:15:46 +03:00 |
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Michel Heily
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e5d93f689f
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Work..
Refactor disassembler to a struct.
Implement more commands;
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2019-06-27 13:15:34 +03:00 |
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Michel Heily
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fc28d89097
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Implement a few debugger commands
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2019-06-27 13:15:34 +03:00 |
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Michel Heily
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107e34aca1
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Start debugger repl
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2019-06-27 13:15:34 +03:00 |
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Michel Heily
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9330c53957
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Start modeling CPU
Wrote a shallow skeleton of a CPU Core.
Finally made the disassembler a clap subcommand.
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2019-06-27 13:15:19 +03:00 |
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Michel Heily
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377f350e12
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Start arm disassembler
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2019-06-24 16:36:20 +03:00 |
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Michel Heily
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8324c1ed50
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Initial commit
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2019-06-24 16:36:20 +03:00 |
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