Michel Heily
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bd053354cb
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Implement LDR/STR (not tested) and add cycle counting
Former-commit-id: ec9e6bfc2a94291e47d41ff7d839007879d3d694
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2019-06-30 16:59:37 +03:00 |
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Michel Heily
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967ccca8dd
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Mega commit - model CPU pipelining.
I except many bugs to arise..
Former-commit-id: bcc6ea57af803f783b0dd548b50956b3ccda2b1a
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2019-06-29 22:23:12 +03:00 |
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Michel Heily
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c90448075f
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debugger: Fix breakpoint hit message
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2019-06-28 15:07:29 +03:00 |
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Michel Heily
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b9d1d38c2d
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debugger: Few improvements
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2019-06-27 13:16:00 +03:00 |
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