Michel Heily
445835eac8
Update Cargo.lock
...
Former-commit-id: e88adeb5cdf40bf3a4fe1e19b22af590518de180
2019-12-27 16:30:09 +02:00
Yonatan Goldschmidt
60c77869df
Add cpal extern crate
...
I really hope all these additions to Cargo.lock are actually its deps...
Former-commit-id: 7c85f330ea3c27f8ebae7020dc4a46d7d557affd
2019-12-20 15:11:26 +02:00
Michel Heily
b288625b9a
Improve the debugger
...
- Add tracing of opcodes and potentially more stuff
- Add option to run a script file at the beginnig (I use it to redirect
traces to a file)
- Support breakpoints again
Former-commit-id: 4e988d6bc1a59456c96547f0320a6d9abedcae00
2019-11-16 18:17:53 +02:00
Michel Heily
bfee970592
Update Cargo.lock
...
Former-commit-id: 91eeaeccafc9eee20aee6b103176b4ee9d42c742
2019-11-09 19:44:55 +02:00
Michel Heily
639993edd7
Add blending and mosaic SFX, and cleanup code.
...
Former-commit-id: b9f0ccaf1820da61f49ebeb2af5beff5cccd722f
2019-08-13 22:15:36 +03:00
Michel Heily
c7dd713605
The big ioregs refactoring.
...
This commit refactors the ioregs:
* Use bitfield crate to implement the GPU ioregs.
* IoRegs are stored in their own variables bindings (i.e, Gpu related ioregs are now fields of the Gpu struct)
- This optimize performance quiet alot from my testings - since every scanline was accessing deseralizing ioregs from sysbus. (Getting constant 59fps now)
* For now, comment out DMA model
Also, cleaned the code up to eliminate rustc warnings.
Former-commit-id: 9077695c446ebd1a71783acfdd9819245aa02d7a
2019-08-03 00:24:15 +03:00
Michel Heily
7e9c0e31da
Add minifb backend - Armwrestler now plays !
...
Former-commit-id: d72ea9139e04624322cf3bc4a8ab330f6bb133a4
2019-07-20 23:02:18 +03:00
Michel Heily
1084be52b8
WIP mode0 rendering
...
Former-commit-id: 6bce375f9373bbddf4522da5ecc2ea3584373847
2019-07-15 19:23:16 +03:00
Michel Heily
efb5d361d6
Add PaletteView command for the debugger.
...
Former-commit-id: c4e0250eea700cfbcbb9f904cde7b6bc055d3e05
2019-07-06 16:04:43 +03:00
Michel Heily
cbddeffd91
arm: Implement MSR_REG and fix some prefetching errors
...
Former-commit-id: 177b8966159ed86472b0d4d031363df72d46807a
2019-07-02 16:53:29 +03:00
Michel Heily
967ccca8dd
Mega commit - model CPU pipelining.
...
I except many bugs to arise..
Former-commit-id: bcc6ea57af803f783b0dd548b50956b3ccda2b1a
2019-06-29 22:23:12 +03:00
Michel Heily
a70b92d5a4
Rename project
2019-06-27 13:15:46 +03:00
Michel Heily
e5d93f689f
Work..
...
Refactor disassembler to a struct.
Implement more commands;
2019-06-27 13:15:34 +03:00
Michel Heily
fc28d89097
Implement a few debugger commands
2019-06-27 13:15:34 +03:00
Michel Heily
107e34aca1
Start debugger repl
2019-06-27 13:15:34 +03:00
Michel Heily
9330c53957
Start modeling CPU
...
Wrote a shallow skeleton of a CPU Core.
Finally made the disassembler a clap subcommand.
2019-06-27 13:15:19 +03:00
Michel Heily
377f350e12
Start arm disassembler
2019-06-24 16:36:20 +03:00
Michel Heily
8324c1ed50
Initial commit
2019-06-24 16:36:20 +03:00
