5 commits

Author	SHA1	Message	Date
Michel Heily	c72bbb96fd	[WIP] Timers ... Seems to work, but the cycle's are not accurate so they run slowly Former-commit-id: a0b80acb4b68ed64caa535a0ec9f75a081d3aed4	2019-08-05 09:53:41 +03:00
Michel Heily	c7dd713605	The big ioregs refactoring. ... This commit refactors the ioregs: * Use bitfield crate to implement the GPU ioregs. * IoRegs are stored in their own variables bindings (i.e, Gpu related ioregs are now fields of the Gpu struct) - This optimize performance quiet alot from my testings - since every scanline was accessing deseralizing ioregs from sysbus. (Getting constant 59fps now) * For now, comment out DMA model Also, cleaned the code up to eliminate rustc warnings. Former-commit-id: 9077695c446ebd1a71783acfdd9819245aa02d7a	2019-08-03 00:24:15 +03:00
Michel Heily	9f0df9af06	optimization: Optimize VRAM accesses from within the gpu. ... Not going through the memory mapping anymore. Also, this commit wraps the gpu pixeldata with a struct Former-commit-id: d7b706d9de61bac7909e10d6bbe092968e6acc9f	2019-08-02 18:04:35 +03:00
Michel Heily	e962150aaf	Start working on Interrupts. ... it kinda works now, but needs testing. Former-commit-id: 8510314cce248a737d492d935cf5b48f86d920ed	2019-07-29 01:28:22 +03:00
Michel Heily	53115a9a58	Refactor core functionality into a separate module ... Former-commit-id: 5d55b9eb0b63ed7c61465b4e814782165caa5002	2019-07-20 16:46:00 +03:00

Renamed from src/sysbus.rs (Browse further)