0665ff7451
Former-commit-id: 8a103161f34eb1a6c731c63ae65ca1056117ec55 Former-commit-id: 74c8158e7354253f6bd4ad50488d34de34e3ad70
293 lines
12 KiB
Rust
293 lines
12 KiB
Rust
use std::env;
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use std::fs;
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use std::io::Write;
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use std::path::Path;
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extern crate bit;
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use bit::BitIndex;
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// copied and slightly adjusted from src/core/arm7tdmi/thumb/mod.rs
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fn thumb_decode(i: u16) -> &'static str {
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if i & 0xf800 == 0x1800 {
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"AddSub"
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} else if i & 0xe000 == 0x0000 {
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"MoveShiftedReg"
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} else if i & 0xe000 == 0x2000 {
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"DataProcessImm"
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} else if i & 0xfc00 == 0x4000 {
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"AluOps"
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} else if i & 0xfc00 == 0x4400 {
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"HiRegOpOrBranchExchange"
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} else if i & 0xf800 == 0x4800 {
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"LdrPc"
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} else if i & 0xf200 == 0x5000 {
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"LdrStrRegOffset"
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} else if i & 0xf200 == 0x5200 {
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"LdrStrSHB"
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} else if i & 0xe000 == 0x6000 {
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"LdrStrImmOffset"
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} else if i & 0xf000 == 0x8000 {
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"LdrStrHalfWord"
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} else if i & 0xf000 == 0x9000 {
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"LdrStrSp"
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} else if i & 0xf000 == 0xa000 {
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"LoadAddress"
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} else if i & 0xff00 == 0xb000 {
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"AddSp"
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} else if i & 0xf600 == 0xb400 {
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"PushPop"
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} else if i & 0xf000 == 0xc000 {
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"LdmStm"
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} else if i & 0xff00 == 0xdf00 {
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"Swi"
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} else if i & 0xf000 == 0xd000 {
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"BranchConditional"
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} else if i & 0xf800 == 0xe000 {
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"Branch"
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} else if i & 0xf000 == 0xf000 {
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"BranchLongWithLink"
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} else {
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"Undefined"
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}
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}
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trait BitAsInt<T: From<bool>>: BitIndex {
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fn ibit(&self, i: usize) -> T {
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self.bit(i).into()
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}
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}
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impl BitAsInt<u32> for u32 {}
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/// Returns a string representation of rustboyadvance_ng::core::arm7tdmi::arm::ArmFormat enum member
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/// # Arguments
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/// * `i` - A 32bit ARM instruction
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///
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/// Decoding is according to this table from http://problemkaputt.de/gbatek.htm#ARMBinaryOpcodeFormat
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/// ```
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/// |..3 ..................2 ..................1 ..................0|
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/// |1_0_9_8_7_6_5_4_3_2_1_0_9_8_7_6_5_4_3_2_1_0_9_8_7_6_5_4_3_2_1_0|
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/// |_Cond__|0_0_0|___Op__|S|__Rn___|__Rd___|__Shift__|Typ|0|__Rm___| DataProc
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/// |_Cond__|0_0_0|___Op__|S|__Rn___|__Rd___|__Rs___|0|Typ|1|__Rm___| DataProc
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/// |_Cond__|0_0_1|___Op__|S|__Rn___|__Rd___|_Shift_|___Immediate___| DataProc
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/// |_Cond__|0_0_1_1_0_0_1_0_0_0_0_0_1_1_1_1_0_0_0_0|_____Hint______| ARM11:Hint
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/// |_Cond__|0_0_1_1_0|P|1|0|_Field_|__Rd___|_Shift_|___Immediate___| PSR Imm
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/// |_Cond__|0_0_0_1_0|P|L|0|_Field_|__Rd___|0_0_0_0|0_0_0_0|__Rm___| PSR Reg
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/// |_Cond__|0_0_0_1_0_0_1_0_1_1_1_1_1_1_1_1_1_1_1_1|0_0|L|1|__Rn___| BX,BLX
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/// |1_1_1_0|0_0_0_1_0_0_1_0|_____immediate_________|0_1_1_1|_immed_| ARM9:BKPT
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/// |_Cond__|0_0_0_1_0_1_1_0_1_1_1_1|__Rd___|1_1_1_1|0_0_0_1|__Rm___| ARM9:CLZ
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/// |_Cond__|0_0_0_1_0|Op_|0|__Rn___|__Rd___|0_0_0_0|0_1_0_1|__Rm___| ARM9:QALU
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/// |_Cond__|0_0_0_0_0_0|A|S|__Rd___|__Rn___|__Rs___|1_0_0_1|__Rm___| Multiply
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/// |_Cond__|0_0_0_0_0_1_0_0|_RdHi__|_RdLo__|__Rs___|1_0_0_1|__Rm___| ARM11:UMAAL
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/// |_Cond__|0_0_0_0_1|U|A|S|_RdHi__|_RdLo__|__Rs___|1_0_0_1|__Rm___| MulLong
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/// |_Cond__|0_0_0_1_0|Op_|0|Rd/RdHi|Rn/RdLo|__Rs___|1|y|x|0|__Rm___| MulHalfARM9
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/// |_Cond__|0_0_0_1_0|B|0_0|__Rn___|__Rd___|0_0_0_0|1_0_0_1|__Rm___| TransSwp12
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/// |_Cond__|0_0_0_1_1|_Op__|__Rn___|__Rd___|1_1_1_1|1_0_0_1|__Rm___| ARM11:LDREX
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/// |_Cond__|0_0_0|P|U|0|W|L|__Rn___|__Rd___|0_0_0_0|1|S|H|1|__Rm___| TransReg10
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/// |_Cond__|0_0_0|P|U|1|W|L|__Rn___|__Rd___|OffsetH|1|S|H|1|OffsetL| TransImm10
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/// |_Cond__|0_1_0|P|U|B|W|L|__Rn___|__Rd___|_________Offset________| TransImm9
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/// |_Cond__|0_1_1|P|U|B|W|L|__Rn___|__Rd___|__Shift__|Typ|0|__Rm___| TransReg9
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/// |_Cond__|0_1_1|________________xxx____________________|1|__xxx__| Undefined
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/// |_Cond__|0_1_1|Op_|x_x_x_x_x_x_x_x_x_x_x_x_x_x_x_x_x_x|1|x_x_x_x| ARM11:Media
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/// |1_1_1_1_0_1_0_1_0_1_1_1_1_1_1_1_1_1_1_1_0_0_0_0_0_0_0_1_1_1_1_1| ARM11:CLREX
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/// |_Cond__|1_0_0|P|U|S|W|L|__Rn___|__________Register_List________| BlockTrans
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/// |_Cond__|1_0_1|L|___________________Offset______________________| B,BL,BLX
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/// |_Cond__|1_1_0|P|U|N|W|L|__Rn___|__CRd__|__CP#__|____Offset_____| CoDataTrans
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/// |_Cond__|1_1_0_0_0_1_0|L|__Rn___|__Rd___|__CP#__|_CPopc_|__CRm__| CoRR ARM9
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/// |_Cond__|1_1_1_0|_CPopc_|__CRn__|__CRd__|__CP#__|_CP__|0|__CRm__| CoDataOp
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/// |_Cond__|1_1_1_0|CPopc|L|__CRn__|__Rd___|__CP#__|_CP__|1|__CRm__| CoRegTrans
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/// |_Cond__|1_1_1_1|_____________Ignored_by_Processor______________| SWI
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/// ```
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fn arm_decode(i: u32) -> String {
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const T: bool = true;
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const F: bool = false;
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// First, decode the the top-most non-condition bits
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match i.bit_range(26..28) {
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0b00 => {
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/* DataProcessing and friends */
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let result: Option<String> = match (i.bit_range(23..26), i.bit_range(4..8)) {
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(0b000, 0b1001) => {
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if 0b0 == i.ibit(22) {
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Some(String::from("exec_arm_mul_mla"))
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} else {
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None
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}
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}
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(0b001, 0b1001) => Some(String::from("exec_arm_mull_mlal")),
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(0b010, 0b1001) => {
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if 0b00 == i.bit_range(20..22) {
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Some(String::from("exec_arm_swp"))
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} else {
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None
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}
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}
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(0b010, 0b0001) => {
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if 0b010 == i.bit_range(20..23) {
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Some(format!("exec_arm_bx"))
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} else {
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None
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}
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}
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_ => None,
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};
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result.unwrap_or_else(|| {
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match (i.ibit(25), i.ibit(22), i.ibit(7), i.ibit(4)) {
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(0, 0, 1, 1) => String::from("exec_arm_ldr_str_hs_reg"),
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(0, 1, 1, 1) => String::from("exec_arm_ldr_str_hs_imm"),
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_ => {
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let set_cond_flags = i.bit(20);
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// PSR Transfers are encoded as a subset of Data Processing,
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// with S bit OFF and the encode opcode is one of TEQ,CMN,TST,CMN
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let is_op_not_touching_rd = i.bit_range(21..25) & 0b1100 == 0b1000;
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if !set_cond_flags && is_op_not_touching_rd {
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if i.bit(21) {
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// Since bit-16 is ignored and we can't know statically if this is a exec_arm_transfer_to_status or exec_arm_transfer_to_status
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String::from("exec_arm_transfer_to_status")
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} else {
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String::from("exec_arm_mrs")
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}
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} else {
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format!("exec_arm_data_processing::<{OP}, {IMM}, {SET_FLAGS}, {SHIFT_BY_REG}>",
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OP=i.bit_range(21..25),
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IMM=i.bit(25),
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SET_FLAGS=i.bit(20),
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SHIFT_BY_REG=i.bit(4))
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}
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}
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}
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})
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}
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0b01 => {
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match (i.bit(25), i.bit(4)) {
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(_, F) | (F, T) => format!(
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"exec_arm_ldr_str::<{LOAD}, {WRITEBACK}, {PRE_INDEX}, {BYTE}, {SHIFT}, {ADD}, {BS_OP}, {SHIFT_BY_REG}>",
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LOAD = i.bit(20),
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WRITEBACK = i.bit(21),
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BYTE = i.bit(22),
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ADD = i.bit(23),
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PRE_INDEX = i.bit(24),
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SHIFT = i.bit(25),
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BS_OP = i.bit_range(5..7) as u8,
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SHIFT_BY_REG = i.bit(4),
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),
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(T, T) => String::from("arm_undefined"), /* Possible ARM11 but we don't implement these */
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}
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}
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0b10 => match i.bit(25) {
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F => String::from("exec_arm_ldm_stm"),
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T => format!("exec_arm_b_bl::<{LINK}>", LINK = i.bit(24)),
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},
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0b11 => {
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match (i.ibit(25), i.ibit(24), i.ibit(4)) {
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(0b0, _, _) => String::from("arm_undefined"), /* CoprocessorDataTransfer not implemented */
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(0b1, 0b0, 0b0) => String::from("arm_undefined"), /* CoprocessorDataOperation not implemented */
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(0b1, 0b0, 0b1) => String::from("arm_undefined"), /* CoprocessorRegisterTransfer not implemented */
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(0b1, 0b1, _) => String::from("exec_arm_swi"),
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_ => String::from("arm_undefined"),
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}
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}
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_ => unreachable!(),
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}
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}
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fn thumb_format_to_handler(thumb_fmt: &str) -> &'static str {
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match thumb_fmt {
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"MoveShiftedReg" => "exec_thumb_move_shifted_reg",
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"AddSub" => "exec_thumb_add_sub",
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"DataProcessImm" => "exec_thumb_data_process_imm",
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"AluOps" => "exec_thumb_alu_ops",
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"HiRegOpOrBranchExchange" => "exec_thumb_hi_reg_op_or_bx",
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"LdrPc" => "exec_thumb_ldr_pc",
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"LdrStrRegOffset" => "exec_thumb_ldr_str_reg_offset",
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"LdrStrSHB" => "exec_thumb_ldr_str_shb",
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"LdrStrImmOffset" => "exec_thumb_ldr_str_imm_offset",
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"LdrStrHalfWord" => "exec_thumb_ldr_str_halfword",
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"LdrStrSp" => "exec_thumb_ldr_str_sp",
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"LoadAddress" => "exec_thumb_load_address",
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"AddSp" => "exec_thumb_add_sp",
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"PushPop" => "exec_thumb_push_pop",
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"LdmStm" => "exec_thumb_ldm_stm",
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"BranchConditional" => "exec_thumb_branch_with_cond",
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"Swi" => "exec_thumb_swi",
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"Branch" => "exec_thumb_branch",
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"BranchLongWithLink" => "exec_thumb_branch_long_with_link",
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"Undefined" => "thumb_undefined",
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_ => unreachable!(),
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}
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}
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fn generate_thumb_lut(file: &mut fs::File) -> Result<(), std::io::Error> {
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writeln!(file, "impl<I: MemoryInterface> Core<I> {{")?;
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writeln!(
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file,
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" pub const THUMB_LUT: [ThumbInstructionInfo<I>; 1024] = ["
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)?;
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for i in 0..1024 {
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let thumb_fmt = thumb_decode(i << 6);
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let handler_name = thumb_format_to_handler(thumb_fmt);
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writeln!(
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file,
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" /* {:#x} */
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ThumbInstructionInfo {{
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handler_fn: Core::{},
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#[cfg(feature = \"debugger\")]
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fmt: ThumbFormat::{},
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}},",
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i, handler_name, thumb_fmt
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)?;
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}
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writeln!(file, " ];")?;
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writeln!(file, "}}")?;
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Ok(())
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}
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fn generate_arm_lut(file: &mut fs::File) -> Result<(), std::io::Error> {
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writeln!(file, "impl<I: MemoryInterface> Core<I> {{")?;
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writeln!(
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file,
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" pub const ARM_LUT: [ArmInstructionInfo<I>; 4096] = ["
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)?;
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for i in 0..4096 {
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let handler_name = arm_decode(((i & 0xff0) << 16) | ((i & 0x00f) << 4));
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writeln!(
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file,
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" /* {:#x} */
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ArmInstructionInfo {{
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handler_fn: Core::{},
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#[cfg(feature = \"debugger\")]
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fmt: ArmFormat::Undefined,
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}} ,",
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i, handler_name
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)?;
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}
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writeln!(file, " ];")?;
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writeln!(file, "}}")?;
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Ok(())
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}
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fn main() {
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let arm7tdmi_dispatch_table_enabled =
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env::var_os("CARGO_FEATURE_ARM7TDMI_DISPATCH_TABLE").is_some();
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if arm7tdmi_dispatch_table_enabled {
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// TODO - don't do this in the build script and use `const fn` instead when it becomes stable
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let out_dir = env::var_os("OUT_DIR").unwrap();
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let thumb_lut_path = Path::new(&out_dir).join("thumb_lut.rs");
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let mut thumb_lut_file = fs::File::create(&thumb_lut_path).expect("failed to create file");
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generate_thumb_lut(&mut thumb_lut_file).expect("failed to generate thumb table");
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let arm_lut_path = Path::new(&out_dir).join("arm_lut.rs");
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let mut arm_lut_file = fs::File::create(&arm_lut_path).expect("failed to create file");
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generate_arm_lut(&mut arm_lut_file).expect("failed to generate arm table");
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println!("cargo:rerun-if-changed=build.rs");
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}
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}
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