28fb9ffa70
Been wanting to do this for a long time. This does impose performance issues when building with the vanilla release profile, as cargo does not perform optimizations across crate boundary (we care mostly about inlining). so I added release-lto profile Also fixed some broken stuff I found across the project, meh Former-commit-id: 06d03263cc6245313f3ea22c715479ab6da7c4d4 Former-commit-id: f93abd10c67ea8a3b8072b47462be5eca4f3e02b
551 lines
20 KiB
Rust
551 lines
20 KiB
Rust
use serde::{Deserialize, Serialize};
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use super::arm7tdmi::memory::*;
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use super::bios::Bios;
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use super::bus::*;
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use super::cartridge::Cartridge;
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use super::dma::DmaNotifer;
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use super::iodev::{IoDevices, WaitControl};
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use super::sched::*;
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use arm7tdmi::{self, Arm7tdmiCore};
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use rustboyadvance_utils::{Shared, WeakPointer};
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pub mod consts {
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pub const WORK_RAM_SIZE: usize = 256 * 1024;
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pub const INTERNAL_RAM_SIZE: usize = 32 * 1024;
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pub const BIOS_ADDR: u32 = 0x0000_0000;
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pub const EWRAM_ADDR: u32 = 0x0200_0000;
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pub const IWRAM_ADDR: u32 = 0x0300_0000;
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pub const IOMEM_ADDR: u32 = 0x0400_0000;
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pub const PALRAM_ADDR: u32 = 0x0500_0000;
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pub const VRAM_ADDR: u32 = 0x0600_0000;
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pub const OAM_ADDR: u32 = 0x0700_0000;
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pub const GAMEPAK_WS0_LO: u32 = 0x0800_0000;
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pub const GAMEPAK_WS0_HI: u32 = 0x0900_0000;
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pub const GAMEPAK_WS1_LO: u32 = 0x0A00_0000;
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pub const GAMEPAK_WS1_HI: u32 = 0x0B00_0000;
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pub const GAMEPAK_WS2_LO: u32 = 0x0C00_0000;
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pub const GAMEPAK_WS2_HI: u32 = 0x0D00_0000;
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pub const SRAM_LO: u32 = 0x0E00_0000;
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pub const SRAM_HI: u32 = 0x0F00_0000;
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pub const PAGE_BIOS: usize = (BIOS_ADDR >> 24) as usize;
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pub const PAGE_EWRAM: usize = (EWRAM_ADDR >> 24) as usize;
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pub const PAGE_IWRAM: usize = (IWRAM_ADDR >> 24) as usize;
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pub const PAGE_IOMEM: usize = (IOMEM_ADDR >> 24) as usize;
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pub const PAGE_PALRAM: usize = (PALRAM_ADDR >> 24) as usize;
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pub const PAGE_VRAM: usize = (VRAM_ADDR >> 24) as usize;
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pub const PAGE_OAM: usize = (OAM_ADDR >> 24) as usize;
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pub const PAGE_GAMEPAK_WS0: usize = (GAMEPAK_WS0_LO >> 24) as usize;
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pub const PAGE_GAMEPAK_WS1: usize = (GAMEPAK_WS1_LO >> 24) as usize;
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pub const PAGE_GAMEPAK_WS2: usize = (GAMEPAK_WS2_LO >> 24) as usize;
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pub const PAGE_SRAM_LO: usize = (SRAM_LO >> 24) as usize;
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pub const PAGE_SRAM_HI: usize = (SRAM_HI >> 24) as usize;
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}
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use consts::*;
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// Only the first 15 entries are actually used, the rest are dummy entries for open-bus
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const CYCLE_LUT_SIZE: usize = 0x100;
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#[derive(Serialize, Deserialize, Clone)]
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struct CycleLookupTables {
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n_cycles32: Box<[usize]>,
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s_cycles32: Box<[usize]>,
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n_cycles16: Box<[usize]>,
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s_cycles16: Box<[usize]>,
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}
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impl Default for CycleLookupTables {
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fn default() -> CycleLookupTables {
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CycleLookupTables {
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n_cycles32: vec![1; CYCLE_LUT_SIZE].into_boxed_slice(),
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s_cycles32: vec![1; CYCLE_LUT_SIZE].into_boxed_slice(),
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n_cycles16: vec![1; CYCLE_LUT_SIZE].into_boxed_slice(),
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s_cycles16: vec![1; CYCLE_LUT_SIZE].into_boxed_slice(),
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}
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}
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}
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impl CycleLookupTables {
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pub fn init(&mut self) {
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self.n_cycles32[PAGE_EWRAM] = 6;
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self.s_cycles32[PAGE_EWRAM] = 6;
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self.n_cycles16[PAGE_EWRAM] = 3;
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self.s_cycles16[PAGE_EWRAM] = 3;
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self.n_cycles32[PAGE_OAM] = 2;
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self.s_cycles32[PAGE_OAM] = 2;
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self.n_cycles16[PAGE_OAM] = 1;
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self.s_cycles16[PAGE_OAM] = 1;
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self.n_cycles32[PAGE_VRAM] = 2;
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self.s_cycles32[PAGE_VRAM] = 2;
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self.n_cycles16[PAGE_VRAM] = 1;
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self.s_cycles16[PAGE_VRAM] = 1;
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self.n_cycles32[PAGE_PALRAM] = 2;
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self.s_cycles32[PAGE_PALRAM] = 2;
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self.n_cycles16[PAGE_PALRAM] = 1;
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self.s_cycles16[PAGE_PALRAM] = 1;
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}
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pub fn update_gamepak_waitstates(&mut self, waitcnt: WaitControl) {
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static S_GAMEPAK_NSEQ_CYCLES: [usize; 4] = [4, 3, 2, 8];
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static S_GAMEPAK_WS0_SEQ_CYCLES: [usize; 2] = [2, 1];
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static S_GAMEPAK_WS1_SEQ_CYCLES: [usize; 2] = [4, 1];
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static S_GAMEPAK_WS2_SEQ_CYCLES: [usize; 2] = [8, 1];
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let ws0_first_access = waitcnt.ws0_first_access() as usize;
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let ws1_first_access = waitcnt.ws1_first_access() as usize;
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let ws2_first_access = waitcnt.ws2_first_access() as usize;
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let ws0_second_access = waitcnt.ws0_second_access() as usize;
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let ws1_second_access = waitcnt.ws1_second_access() as usize;
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let ws2_second_access = waitcnt.ws2_second_access() as usize;
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// update SRAM access
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let sram_wait_cycles = 1 + S_GAMEPAK_NSEQ_CYCLES[waitcnt.sram_wait_control() as usize];
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self.n_cycles32[PAGE_SRAM_LO] = sram_wait_cycles;
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self.n_cycles32[PAGE_SRAM_LO] = sram_wait_cycles;
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self.n_cycles16[PAGE_SRAM_HI] = sram_wait_cycles;
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self.n_cycles16[PAGE_SRAM_HI] = sram_wait_cycles;
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self.s_cycles32[PAGE_SRAM_LO] = sram_wait_cycles;
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self.s_cycles32[PAGE_SRAM_LO] = sram_wait_cycles;
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self.s_cycles16[PAGE_SRAM_HI] = sram_wait_cycles;
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self.s_cycles16[PAGE_SRAM_HI] = sram_wait_cycles;
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// update both pages of each waitstate
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for i in 0..2 {
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self.n_cycles16[PAGE_GAMEPAK_WS0 + i] = 1 + S_GAMEPAK_NSEQ_CYCLES[ws0_first_access];
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self.s_cycles16[PAGE_GAMEPAK_WS0 + i] = 1 + S_GAMEPAK_WS0_SEQ_CYCLES[ws0_second_access];
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self.n_cycles16[PAGE_GAMEPAK_WS1 + i] = 1 + S_GAMEPAK_NSEQ_CYCLES[ws1_first_access];
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self.s_cycles16[PAGE_GAMEPAK_WS1 + i] = 1 + S_GAMEPAK_WS1_SEQ_CYCLES[ws1_second_access];
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self.n_cycles16[PAGE_GAMEPAK_WS2 + i] = 1 + S_GAMEPAK_NSEQ_CYCLES[ws2_first_access];
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self.s_cycles16[PAGE_GAMEPAK_WS2 + i] = 1 + S_GAMEPAK_WS2_SEQ_CYCLES[ws2_second_access];
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// ROM 32bit accesses are split into two 16bit accesses 1N+1S
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self.n_cycles32[PAGE_GAMEPAK_WS0 + i] =
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self.n_cycles16[PAGE_GAMEPAK_WS0 + i] + self.s_cycles16[PAGE_GAMEPAK_WS0 + i];
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self.n_cycles32[PAGE_GAMEPAK_WS1 + i] =
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self.n_cycles16[PAGE_GAMEPAK_WS1 + i] + self.s_cycles16[PAGE_GAMEPAK_WS1 + i];
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self.n_cycles32[PAGE_GAMEPAK_WS2 + i] =
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self.n_cycles16[PAGE_GAMEPAK_WS2 + i] + self.s_cycles16[PAGE_GAMEPAK_WS2 + i];
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self.s_cycles32[PAGE_GAMEPAK_WS0 + i] = 2 * self.s_cycles16[PAGE_GAMEPAK_WS0 + i];
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self.s_cycles32[PAGE_GAMEPAK_WS1 + i] = 2 * self.s_cycles16[PAGE_GAMEPAK_WS1 + i];
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self.s_cycles32[PAGE_GAMEPAK_WS2 + i] = 2 * self.s_cycles16[PAGE_GAMEPAK_WS2 + i];
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}
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}
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}
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#[derive(Clone)]
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pub struct SysBus {
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pub io: Shared<IoDevices>,
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scheduler: Shared<Scheduler>,
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arm_core: WeakPointer<Arm7tdmiCore<SysBus>>,
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bios: Bios,
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ewram: Box<[u8]>,
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iwram: Box<[u8]>,
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pub cartridge: Cartridge,
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cycle_luts: CycleLookupTables,
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pub trace_access: bool,
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}
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pub type SysBusPtr = WeakPointer<SysBus>;
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impl SchedulerConnect for SysBus {
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fn connect_scheduler(&mut self, scheduler: SharedScheduler) {
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self.scheduler = scheduler.clone();
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self.io.connect_scheduler(scheduler.clone());
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}
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}
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impl SysBus {
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pub fn new_with_memories(
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scheduler: Shared<Scheduler>,
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io: Shared<IoDevices>,
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cartridge: Cartridge,
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bios_rom: Box<[u8]>,
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ewram: Box<[u8]>,
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iwram: Box<[u8]>,
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) -> SysBus {
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let mut luts = CycleLookupTables::default();
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luts.init();
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luts.update_gamepak_waitstates(io.waitcnt);
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SysBus {
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io,
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scheduler,
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arm_core: WeakPointer::default(),
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cartridge,
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bios: Bios::new(bios_rom),
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ewram,
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iwram,
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cycle_luts: luts,
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trace_access: false,
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}
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}
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pub fn new(
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scheduler: Shared<Scheduler>,
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io: Shared<IoDevices>,
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bios_rom: Box<[u8]>,
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cartridge: Cartridge,
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) -> SysBus {
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let ewram = vec![0; WORK_RAM_SIZE].into_boxed_slice();
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let iwram = vec![0; INTERNAL_RAM_SIZE].into_boxed_slice();
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SysBus::new_with_memories(scheduler, io, cartridge, bios_rom, ewram, iwram)
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}
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pub fn set_ewram(&mut self, buffer: Box<[u8]>) {
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self.ewram = buffer;
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}
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pub fn set_iwram(&mut self, buffer: Box<[u8]>) {
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self.iwram = buffer;
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}
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pub fn get_ewram(&self) -> &[u8] {
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&self.ewram
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}
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pub fn get_iwram(&self) -> &[u8] {
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&self.iwram
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}
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pub fn set_io_devices(&mut self, io_devs: Shared<IoDevices>) {
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self.io = io_devs;
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}
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/// must be called whenever this object is instanciated
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pub fn init(&mut self, arm_core: WeakPointer<Arm7tdmiCore<SysBus>>) {
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self.arm_core = arm_core.clone();
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self.bios.connect_arm_core(arm_core.clone());
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let ptr = SysBusPtr::new(self as *mut SysBus);
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// HACK
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self.io.set_sysbus_ptr(ptr.clone());
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}
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pub fn on_waitcnt_written(&mut self, waitcnt: WaitControl) {
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self.cycle_luts.update_gamepak_waitstates(waitcnt);
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}
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pub fn idle_cycle(&mut self) {
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self.scheduler.update(1);
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}
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#[inline(always)]
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pub fn add_cycles(&mut self, addr: Addr, access: MemoryAccess, width: MemoryAccessWidth) {
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use MemoryAccess::*;
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use MemoryAccessWidth::*;
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let page = ((addr >> 24) & 0xF) as usize;
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let cycles = unsafe {
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match width {
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MemoryAccess8 | MemoryAccess16 => match access {
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NonSeq => self.cycle_luts.n_cycles16.get_unchecked(page),
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Seq => self.cycle_luts.s_cycles16.get_unchecked(page),
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},
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MemoryAccess32 => match access {
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NonSeq => self.cycle_luts.n_cycles32.get_unchecked(page),
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Seq => self.cycle_luts.s_cycles32.get_unchecked(page),
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},
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}
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};
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self.scheduler.update(*cycles);
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}
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/// Helper for "open-bus" accesses
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/// http://problemkaputt.de/gbatek.htm#gbaunpredictablethings
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/// Reading from Unused Memory (00004000-01FFFFFF,10000000-FFFFFFFF)
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/// `addr` is considered to be an address of
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fn read_invalid(&mut self, addr: Addr) -> u32 {
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warn!("invalid read @{:08x}", addr);
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let value = match self.arm_core.cpsr.state() {
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arm7tdmi::CpuState::ARM => self.arm_core.get_prefetched_opcode(),
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arm7tdmi::CpuState::THUMB => {
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// For THUMB code the result consists of two 16bit fragments and depends on the address area
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// and alignment where the opcode was stored.
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let decoded = self.arm_core.get_decoded_opcode() & 0xffff; // [$+2]
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let prefetched = self.arm_core.get_prefetched_opcode() & 0xffff; // [$+4]
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let r15 = self.arm_core.pc;
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let mut value = prefetched;
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match (r15 >> 24) as usize {
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PAGE_BIOS | PAGE_OAM => {
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// TODO this is probably wrong, according to GBATEK, we should be using $+6 here but it isn't prefetched yet.
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value = value << 16;
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value |= decoded;
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}
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PAGE_IWRAM => {
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// OldLO=[$+2], OldHI=[$+2]
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if r15 & 3 == 0 {
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// LSW = [$+4], MSW = OldHI ;for opcodes at 4-byte aligned locations
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value |= decoded << 16;
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} else {
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// LSW = OldLO, MSW = [$+4] ;for opcodes at non-4-byte aligned locations
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value = value << 16;
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value |= decoded;
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}
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}
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_ => value |= value << 16,
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}
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value
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}
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};
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value >> ((addr & 3) << 3)
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}
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}
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/// Todo - implement bound checks for EWRAM/IWRAM
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impl Bus for SysBus {
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#[inline]
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fn read_32(&mut self, addr: Addr) -> u32 {
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match addr & 0xff000000 {
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BIOS_ADDR => {
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if addr <= 0x3ffc {
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self.bios.read_32(addr)
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} else {
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self.read_invalid(addr)
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}
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}
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EWRAM_ADDR => self.ewram.read_32(addr & 0x3_fffc),
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IWRAM_ADDR => self.iwram.read_32(addr & 0x7ffc),
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IOMEM_ADDR => {
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let addr = if addr & 0xfffc == 0x8000 {
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0x800
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} else {
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addr & 0x00fffffc
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};
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self.io.read_32(addr)
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}
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PALRAM_ADDR | VRAM_ADDR | OAM_ADDR => self.io.gpu.read_32(addr),
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GAMEPAK_WS0_LO | GAMEPAK_WS0_HI | GAMEPAK_WS1_LO | GAMEPAK_WS1_HI | GAMEPAK_WS2_LO => {
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self.cartridge.read_32(addr)
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}
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GAMEPAK_WS2_HI => self.cartridge.read_32(addr),
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SRAM_LO | SRAM_HI => self.cartridge.read_32(addr),
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_ => self.read_invalid(addr),
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}
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}
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#[inline]
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fn read_16(&mut self, addr: Addr) -> u16 {
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match addr & 0xff000000 {
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BIOS_ADDR => {
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if addr <= 0x3ffe {
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self.bios.read_16(addr)
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} else {
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self.read_invalid(addr) as u16
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}
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}
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EWRAM_ADDR => self.ewram.read_16(addr & 0x3_fffe),
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IWRAM_ADDR => self.iwram.read_16(addr & 0x7ffe),
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IOMEM_ADDR => {
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let addr = if addr & 0xfffe == 0x8000 {
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0x800
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} else {
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addr & 0x00fffffe
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};
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self.io.read_16(addr)
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}
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PALRAM_ADDR | VRAM_ADDR | OAM_ADDR => self.io.gpu.read_16(addr),
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GAMEPAK_WS0_LO | GAMEPAK_WS0_HI | GAMEPAK_WS1_LO | GAMEPAK_WS1_HI | GAMEPAK_WS2_LO => {
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self.cartridge.read_16(addr)
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}
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GAMEPAK_WS2_HI => self.cartridge.read_16(addr),
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SRAM_LO | SRAM_HI => self.cartridge.read_16(addr),
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_ => self.read_invalid(addr) as u16,
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}
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}
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#[inline]
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fn read_8(&mut self, addr: Addr) -> u8 {
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match addr & 0xff000000 {
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BIOS_ADDR => {
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if addr <= 0x3fff {
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self.bios.read_8(addr)
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} else {
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self.read_invalid(addr) as u8
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}
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}
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EWRAM_ADDR => self.ewram.read_8(addr & 0x3_ffff),
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IWRAM_ADDR => self.iwram.read_8(addr & 0x7fff),
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IOMEM_ADDR => {
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let addr = if addr & 0xffff == 0x8000 {
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0x800
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} else {
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addr & 0x00ffffff
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};
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self.io.read_8(addr)
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}
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PALRAM_ADDR | VRAM_ADDR | OAM_ADDR => self.io.gpu.read_8(addr),
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GAMEPAK_WS0_LO | GAMEPAK_WS0_HI | GAMEPAK_WS1_LO | GAMEPAK_WS1_HI | GAMEPAK_WS2_LO => {
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self.cartridge.read_8(addr)
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}
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GAMEPAK_WS2_HI => self.cartridge.read_8(addr),
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SRAM_LO | SRAM_HI => self.cartridge.read_8(addr),
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_ => self.read_invalid(addr) as u8,
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}
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}
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#[inline]
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fn write_32(&mut self, addr: Addr, value: u32) {
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match addr & 0xff000000 {
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BIOS_ADDR => {}
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EWRAM_ADDR => self.ewram.write_32(addr & 0x3_fffc, value),
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IWRAM_ADDR => self.iwram.write_32(addr & 0x7ffc, value),
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IOMEM_ADDR => {
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let addr = if addr & 0xfffc == 0x8000 {
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0x800
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} else {
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addr & 0x00fffffc
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};
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self.io.write_32(addr, value)
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}
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PALRAM_ADDR | VRAM_ADDR | OAM_ADDR => self.io.gpu.write_32(addr, value),
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GAMEPAK_WS0_LO => self.cartridge.write_32(addr, value),
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GAMEPAK_WS2_HI => self.cartridge.write_32(addr, value),
|
|
SRAM_LO | SRAM_HI => self.cartridge.write_32(addr, value),
|
|
_ => {
|
|
// warn!("trying to write invalid address {:#x}", addr);
|
|
// TODO open bus
|
|
}
|
|
}
|
|
}
|
|
|
|
#[inline]
|
|
fn write_16(&mut self, addr: Addr, value: u16) {
|
|
match addr & 0xff000000 {
|
|
BIOS_ADDR => {}
|
|
EWRAM_ADDR => self.ewram.write_16(addr & 0x3_fffe, value),
|
|
IWRAM_ADDR => self.iwram.write_16(addr & 0x7ffe, value),
|
|
IOMEM_ADDR => {
|
|
let addr = if addr & 0xfffe == 0x8000 {
|
|
0x800
|
|
} else {
|
|
addr & 0x00fffffe
|
|
};
|
|
self.io.write_16(addr, value)
|
|
}
|
|
PALRAM_ADDR | VRAM_ADDR | OAM_ADDR => self.io.gpu.write_16(addr, value),
|
|
GAMEPAK_WS0_LO => self.cartridge.write_16(addr, value),
|
|
GAMEPAK_WS2_HI => self.cartridge.write_16(addr, value),
|
|
SRAM_LO | SRAM_HI => self.cartridge.write_16(addr, value),
|
|
_ => {
|
|
// warn!("trying to write invalid address {:#x}", addr);
|
|
// TODO open bus
|
|
}
|
|
}
|
|
}
|
|
|
|
#[inline]
|
|
fn write_8(&mut self, addr: Addr, value: u8) {
|
|
match addr & 0xff000000 {
|
|
BIOS_ADDR => {}
|
|
EWRAM_ADDR => self.ewram.write_8(addr & 0x3_ffff, value),
|
|
IWRAM_ADDR => self.iwram.write_8(addr & 0x7fff, value),
|
|
IOMEM_ADDR => {
|
|
let addr = if addr & 0xffff == 0x8000 {
|
|
0x800
|
|
} else {
|
|
addr & 0x00ffffff
|
|
};
|
|
self.io.write_8(addr, value)
|
|
}
|
|
PALRAM_ADDR | VRAM_ADDR | OAM_ADDR => self.io.gpu.write_8(addr, value),
|
|
GAMEPAK_WS0_LO => self.cartridge.write_8(addr, value),
|
|
GAMEPAK_WS2_HI => self.cartridge.write_8(addr, value),
|
|
SRAM_LO | SRAM_HI => self.cartridge.write_8(addr, value),
|
|
_ => {
|
|
// warn!("trying to write invalid address {:#x}", addr);
|
|
// TODO open bus
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
impl DebugRead for SysBus {
|
|
fn debug_read_8(&mut self, addr: Addr) -> u8 {
|
|
match addr & 0xff000000 {
|
|
BIOS_ADDR => self.bios.debug_read_8(addr),
|
|
EWRAM_ADDR => self.ewram.debug_read_8(addr & 0x3_ffff),
|
|
IWRAM_ADDR => self.iwram.debug_read_8(addr & 0x7fff),
|
|
IOMEM_ADDR => {
|
|
let addr = if addr & 0xffff == 0x8000 {
|
|
0x800
|
|
} else {
|
|
addr & 0x00ffffff
|
|
};
|
|
self.io.debug_read_8(addr)
|
|
}
|
|
PALRAM_ADDR | VRAM_ADDR | OAM_ADDR => self.io.gpu.debug_read_8(addr),
|
|
GAMEPAK_WS0_LO | GAMEPAK_WS0_HI | GAMEPAK_WS1_LO | GAMEPAK_WS1_HI | GAMEPAK_WS2_LO => {
|
|
self.cartridge.debug_read_8(addr)
|
|
}
|
|
GAMEPAK_WS2_HI => self.cartridge.debug_read_8(addr),
|
|
SRAM_LO | SRAM_HI => self.cartridge.debug_read_8(addr),
|
|
_ => {
|
|
// TODO open-bus
|
|
0
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
impl MemoryInterface for SysBus {
|
|
#[inline]
|
|
fn load_8(&mut self, addr: u32, access: MemoryAccess) -> u8 {
|
|
self.add_cycles(addr, access, MemoryAccessWidth::MemoryAccess8);
|
|
self.read_8(addr)
|
|
}
|
|
|
|
#[inline]
|
|
fn load_16(&mut self, addr: u32, access: MemoryAccess) -> u16 {
|
|
self.add_cycles(addr, access, MemoryAccessWidth::MemoryAccess16);
|
|
self.read_16(addr)
|
|
}
|
|
|
|
#[inline]
|
|
fn load_32(&mut self, addr: u32, access: MemoryAccess) -> u32 {
|
|
self.add_cycles(addr, access, MemoryAccessWidth::MemoryAccess32);
|
|
self.read_32(addr)
|
|
}
|
|
|
|
#[inline]
|
|
fn store_8(&mut self, addr: u32, value: u8, access: MemoryAccess) {
|
|
self.add_cycles(addr, access, MemoryAccessWidth::MemoryAccess8);
|
|
self.write_8(addr, value);
|
|
}
|
|
|
|
#[inline]
|
|
fn store_16(&mut self, addr: u32, value: u16, access: MemoryAccess) {
|
|
self.add_cycles(addr, access, MemoryAccessWidth::MemoryAccess8);
|
|
self.write_16(addr, value);
|
|
}
|
|
|
|
#[inline]
|
|
fn store_32(&mut self, addr: u32, value: u32, access: MemoryAccess) {
|
|
self.add_cycles(addr, access, MemoryAccessWidth::MemoryAccess8);
|
|
self.write_32(addr, value);
|
|
}
|
|
|
|
#[inline]
|
|
fn idle_cycle(&mut self) {
|
|
self.scheduler.update(1)
|
|
}
|
|
}
|
|
|
|
impl DmaNotifer for SysBus {
|
|
fn notify(&mut self, timing: u16) {
|
|
self.io.dmac.notify_from_gpu(timing);
|
|
}
|
|
}
|