325 lines
9.6 KiB
Rust
325 lines
9.6 KiB
Rust
use std::fmt;
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use std::ops::Add;
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use byteorder::{LittleEndian, ReadBytesExt, WriteBytesExt};
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use super::arm7tdmi::bus::Bus;
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use super::arm7tdmi::Addr;
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use super::cartridge::Cartridge;
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use super::gpu::GpuState;
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use super::iodev::IoDevices;
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const VIDEO_RAM_SIZE: usize = 128 * 1024;
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const WORK_RAM_SIZE: usize = 256 * 1024;
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const INTERNAL_RAM_SIZE: usize = 32 * 1024;
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const PALETTE_RAM_SIZE: usize = 1 * 1024;
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const OAM_SIZE: usize = 1 * 1024;
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pub const BIOS_ADDR: u32 = 0x0000_0000;
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pub const EWRAM_ADDR: u32 = 0x0200_0000;
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pub const IWRAM_ADDR: u32 = 0x0300_0000;
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pub const IOMEM_ADDR: u32 = 0x0400_0000;
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pub const PALRAM_ADDR: u32 = 0x0500_0000;
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pub const VRAM_ADDR: u32 = 0x0600_0000;
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pub const OAM_ADDR: u32 = 0x0700_0000;
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pub const GAMEPAK_WS0_ADDR: u32 = 0x0800_0000;
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pub const GAMEPAK_MIRROR_WS0_ADDR: u32 = 0x0900_0000;
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pub const GAMEPAK_WS1_ADDR: u32 = 0x0A00_0000;
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pub const GAMEPAK_WS2_ADDR: u32 = 0x0C00_0000;
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#[derive(Debug, Copy, Clone)]
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pub enum MemoryAccessType {
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NonSeq,
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Seq,
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}
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impl fmt::Display for MemoryAccessType {
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fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
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write!(
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f,
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"{}",
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match self {
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MemoryAccessType::NonSeq => "N",
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MemoryAccessType::Seq => "S",
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}
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)
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}
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}
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#[derive(Debug, PartialEq, Copy, Clone)]
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pub enum MemoryAccessWidth {
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MemoryAccess8,
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MemoryAccess16,
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MemoryAccess32,
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}
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impl Add<MemoryAccessWidth> for MemoryAccessType {
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type Output = MemoryAccess;
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fn add(self, other: MemoryAccessWidth) -> Self::Output {
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MemoryAccess(self, other)
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}
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}
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#[derive(Debug, Copy, Clone)]
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pub struct MemoryAccess(pub MemoryAccessType, pub MemoryAccessWidth);
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impl fmt::Display for MemoryAccess {
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fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
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write!(f, "{}-Cycle ({:?})", self.0, self.1)
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}
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}
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#[derive(Debug)]
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pub struct BoxedMemory {
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pub mem: Box<[u8]>,
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}
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impl BoxedMemory {
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pub fn new(boxed_slice: Box<[u8]>) -> BoxedMemory {
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BoxedMemory { mem: boxed_slice }
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}
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}
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impl Bus for BoxedMemory {
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fn read_32(&self, addr: Addr) -> u32 {
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(&self.mem[addr as usize..])
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.read_u32::<LittleEndian>()
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.unwrap()
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}
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fn read_16(&self, addr: Addr) -> u16 {
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(&self.mem[addr as usize..])
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.read_u16::<LittleEndian>()
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.unwrap()
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}
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fn read_8(&self, addr: Addr) -> u8 {
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(&self.mem[addr as usize..])[0]
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}
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fn write_32(&mut self, addr: Addr, value: u32) {
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(&mut self.mem[addr as usize..])
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.write_u32::<LittleEndian>(value)
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.unwrap()
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}
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fn write_16(&mut self, addr: Addr, value: u16) {
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(&mut self.mem[addr as usize..])
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.write_u16::<LittleEndian>(value)
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.unwrap()
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}
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fn write_8(&mut self, addr: Addr, value: u8) {
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(&mut self.mem[addr as usize..]).write_u8(value).unwrap()
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}
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}
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#[derive(Debug)]
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struct DummyBus([u8; 4]);
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impl Bus for DummyBus {
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fn read_32(&self, _addr: Addr) -> u32 {
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0
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}
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fn read_16(&self, _addr: Addr) -> u16 {
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0
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}
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fn read_8(&self, _addr: Addr) -> u8 {
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0
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}
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fn write_32(&mut self, _addr: Addr, _value: u32) {}
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fn write_16(&mut self, _addr: Addr, _value: u16) {}
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fn write_8(&mut self, _addr: Addr, _value: u8) {}
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}
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#[derive(Debug)]
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pub struct SysBus {
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pub io: IoDevices,
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bios: BoxedMemory,
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onboard_work_ram: BoxedMemory,
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internal_work_ram: BoxedMemory,
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pub palette_ram: BoxedMemory,
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pub vram: BoxedMemory,
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pub oam: BoxedMemory,
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gamepak: Cartridge,
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dummy: DummyBus,
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pub trace_access: bool,
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}
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impl SysBus {
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pub fn new(io: IoDevices, bios_rom: Vec<u8>, gamepak: Cartridge) -> SysBus {
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SysBus {
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io: io,
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bios: BoxedMemory::new(bios_rom.into_boxed_slice()),
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onboard_work_ram: BoxedMemory::new(vec![0; WORK_RAM_SIZE].into_boxed_slice()),
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internal_work_ram: BoxedMemory::new(vec![0; INTERNAL_RAM_SIZE].into_boxed_slice()),
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palette_ram: BoxedMemory::new(vec![0; PALETTE_RAM_SIZE].into_boxed_slice()),
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vram: BoxedMemory::new(vec![0; VIDEO_RAM_SIZE].into_boxed_slice()),
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oam: BoxedMemory::new(vec![0; OAM_SIZE].into_boxed_slice()),
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gamepak: gamepak,
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dummy: DummyBus([0; 4]),
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trace_access: false,
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}
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}
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fn map(&self, addr: Addr) -> (&dyn Bus, Addr) {
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let ofs = addr & 0x00ff_ffff;
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match addr & 0xff000000 {
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BIOS_ADDR => {
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if ofs >= 0x4000 {
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(&self.dummy, ofs) // TODO return last fetched opcode
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} else {
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(&self.bios, ofs)
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}
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}
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EWRAM_ADDR => (&self.onboard_work_ram, ofs & 0x3_ffff),
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IWRAM_ADDR => (&self.internal_work_ram, ofs & 0x7fff),
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IOMEM_ADDR => (&self.io, {
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if ofs & 0xffff == 0x8000 {
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0x800
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} else {
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ofs & 0x7ff
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}
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}),
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PALRAM_ADDR => (&self.palette_ram, ofs & 0x3ff),
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VRAM_ADDR => (&self.vram, {
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let mut ofs = ofs & ((VIDEO_RAM_SIZE as u32) - 1);
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if ofs > 0x18000 {
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ofs -= 0x8000;
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}
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ofs
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}),
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OAM_ADDR => (&self.oam, ofs & 0x3ff),
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GAMEPAK_WS0_ADDR | GAMEPAK_MIRROR_WS0_ADDR | GAMEPAK_WS1_ADDR | GAMEPAK_WS2_ADDR => {
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(&self.gamepak, addr & 0x01ff_ffff)
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}
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_ => (&self.dummy, ofs),
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}
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}
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/// TODO proc-macro for generating this function
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fn map_mut(&mut self, addr: Addr) -> (&mut dyn Bus, Addr) {
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let ofs = addr & 0x00ff_ffff;
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match addr & 0xff000000 {
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BIOS_ADDR => (&mut self.dummy, ofs),
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EWRAM_ADDR => (&mut self.onboard_work_ram, ofs & 0x3_ffff),
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IWRAM_ADDR => (&mut self.internal_work_ram, ofs & 0x7fff),
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IOMEM_ADDR => (&mut self.io, {
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if ofs & 0xffff == 0x8000 {
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0x800
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} else {
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ofs & 0x7ff
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}
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}),
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PALRAM_ADDR => (&mut self.palette_ram, ofs & 0x3ff),
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VRAM_ADDR => (&mut self.vram, {
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let mut ofs = ofs & ((VIDEO_RAM_SIZE as u32) - 1);
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if ofs > 0x18000 {
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ofs -= 0x8000;
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}
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ofs
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}),
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OAM_ADDR => (&mut self.oam, ofs & 0x3ff),
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GAMEPAK_WS0_ADDR | GAMEPAK_MIRROR_WS0_ADDR | GAMEPAK_WS1_ADDR | GAMEPAK_WS2_ADDR => {
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(&mut self.gamepak, addr & 0x01ff_ffff)
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}
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_ => (&mut self.dummy, ofs),
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}
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}
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pub fn get_cycles(&self, addr: Addr, access: MemoryAccess) -> usize {
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let nonseq_cycles = [4, 3, 2, 8];
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let seq_cycles = [2, 1];
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let mut cycles = 0;
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// TODO handle EWRAM accesses
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match addr & 0xff000000 {
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EWRAM_ADDR => match access.1 {
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MemoryAccessWidth::MemoryAccess32 => cycles += 6,
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_ => cycles += 3,
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},
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OAM_ADDR | VRAM_ADDR | PALRAM_ADDR => {
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match access.1 {
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MemoryAccessWidth::MemoryAccess32 => cycles += 2,
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_ => cycles += 1,
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}
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if self.io.gpu.state == GpuState::HDraw {
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cycles += 1;
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}
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}
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GAMEPAK_WS0_ADDR | GAMEPAK_MIRROR_WS0_ADDR => match access.0 {
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MemoryAccessType::NonSeq => match access.1 {
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MemoryAccessWidth::MemoryAccess32 => {
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cycles += nonseq_cycles[self.io.waitcnt.ws0_first_access() as usize];
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cycles += seq_cycles[self.io.waitcnt.ws0_second_access() as usize];
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}
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_ => {
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cycles += nonseq_cycles[self.io.waitcnt.ws0_first_access() as usize];
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}
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},
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MemoryAccessType::Seq => {
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cycles += seq_cycles[self.io.waitcnt.ws0_second_access() as usize];
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if access.1 == MemoryAccessWidth::MemoryAccess32 {
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cycles += seq_cycles[self.io.waitcnt.ws0_second_access() as usize];
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}
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}
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},
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GAMEPAK_WS1_ADDR | GAMEPAK_WS2_ADDR => {
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panic!("unimplemented - need to refactor code with a nice macro :(")
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}
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_ => {}
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}
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cycles
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}
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}
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impl Bus for SysBus {
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fn read_32(&self, addr: Addr) -> u32 {
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let (dev, addr) = self.map(addr);
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dev.read_32(addr & 0x1ff_fffc)
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}
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fn read_16(&self, addr: Addr) -> u16 {
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if self.trace_access {
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println!("[TRACE] read_32 addr={:x}", addr);
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}
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let (dev, addr) = self.map(addr);
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dev.read_16(addr & 0x1ff_fffe)
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}
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fn read_8(&self, addr: Addr) -> u8 {
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if self.trace_access {
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println!("[TRACE] read_32 addr={:x}", addr);
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}
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let (dev, addr) = self.map(addr);
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dev.read_8(addr & 0x1ff_ffff)
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}
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fn write_32(&mut self, addr: Addr, value: u32) {
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let (dev, addr) = self.map_mut(addr);
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dev.write_32(addr & 0x1ff_fffc, value);
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}
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fn write_16(&mut self, addr: Addr, value: u16) {
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let (dev, addr) = self.map_mut(addr);
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dev.write_16(addr & 0x1ff_fffe, value);
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}
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fn write_8(&mut self, addr: Addr, value: u8) {
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let (dev, addr) = self.map_mut(addr);
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dev.write_8(addr & 0x1ff_ffff, value);
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}
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}
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