6b8f4e8f51
Former-commit-id: f0223556894a02ad1f85bb81abc18d47b7508445 Former-commit-id: e44b952867197467fa724022a05ba4579b1e2f03
577 lines
18 KiB
Rust
577 lines
18 KiB
Rust
use serde::{Deserialize, Serialize};
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pub use super::exception::Exception;
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use super::{arm::ArmCond, psr::RegPSR, Addr, CpuMode, CpuState};
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use crate::util::{Shared, WeakPointer};
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use super::memory::{MemoryAccess, MemoryInterface};
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use MemoryAccess::*;
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use cfg_if::cfg_if;
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cfg_if! {
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if #[cfg(feature = "arm7tdmi_dispatch_table")] {
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#[cfg(feature = "debugger")]
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use super::thumb::ThumbFormat;
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#[cfg(feature = "debugger")]
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use super::arm::ArmFormat;
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#[cfg_attr(not(feature = "debugger"), repr(transparent))]
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pub struct ThumbInstructionInfo<I: MemoryInterface> {
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pub handler_fn: fn(&mut Core<I>, insn: u16) -> CpuAction,
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#[cfg(feature = "debugger")]
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pub fmt: ThumbFormat,
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}
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#[cfg_attr(not(feature = "debugger"), repr(transparent))]
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pub struct ArmInstructionInfo<I: MemoryInterface> {
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pub handler_fn: fn(&mut Core<I>, insn: u32) -> CpuAction,
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#[cfg(feature = "debugger")]
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pub fmt: ArmFormat,
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}
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} else {
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use super::arm::ArmFormat;
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use super::thumb::ThumbFormat;
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}
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}
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cfg_if! {
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if #[cfg(feature = "debugger")] {
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use super::DecodedInstruction;
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use super::arm::ArmInstruction;
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use super::thumb::ThumbInstruction;
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use super::reg_string;
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use std::fmt;
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use ansi_term::{Colour, Style};
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} else {
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}
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}
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use bit::BitIndex;
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use num::FromPrimitive;
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pub enum CpuAction {
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AdvancePC(MemoryAccess),
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PipelineFlushed,
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}
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#[derive(Serialize, Deserialize, Clone, Debug, Default)]
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pub(super) struct BankedRegisters {
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// r13 and r14 are banked for all modes. System&User mode share them
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pub(super) gpr_banked_r13: [u32; 6],
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pub(super) gpr_banked_r14: [u32; 6],
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// r8-r12 are banked for fiq mode
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pub(super) gpr_banked_old_r8_12: [u32; 5],
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pub(super) gpr_banked_fiq_r8_12: [u32; 5],
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pub(super) spsr_bank: [RegPSR; 6],
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}
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#[derive(Serialize, Deserialize, Clone, Debug)]
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pub struct SavedCpuState {
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pub pc: u32,
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pub gpr: [u32; 15],
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next_fetch_access: MemoryAccess,
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pipeline: [u32; 2],
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pub cpsr: RegPSR,
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pub(super) spsr: RegPSR,
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pub(super) banks: Box<BankedRegisters>,
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pub(super) bs_carry_out: bool,
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}
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#[derive(Clone, Debug)]
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pub struct Core<I: MemoryInterface> {
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pub(super) bus: Shared<I>,
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next_fetch_access: MemoryAccess,
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pipeline: [u32; 2],
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pub pc: u32,
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pub gpr: [u32; 15],
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pub cpsr: RegPSR,
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pub(super) spsr: RegPSR,
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// Todo - do I still need this?
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pub(super) bs_carry_out: bool,
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pub(super) banks: Box<BankedRegisters>, // Putting these in a box so the most-used Cpu fields in the same cacheline
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#[cfg(feature = "debugger")]
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pub last_executed: Option<DecodedInstruction>,
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/// store the gpr before executing an instruction to show diff in the Display impl
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#[cfg(feature = "debugger")]
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gpr_previous: [u32; 15],
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#[cfg(feature = "debugger")]
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pub breakpoints: Vec<u32>,
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#[cfg(feature = "debugger")]
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pub verbose: bool,
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#[cfg(feature = "debugger")]
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pub trace_opcodes: bool,
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#[cfg(feature = "debugger")]
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pub trace_exceptions: bool,
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}
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impl<I: MemoryInterface> Core<I> {
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pub fn new(bus: Shared<I>) -> Core<I> {
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let cpsr = RegPSR::new(0x0000_00D3);
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Core {
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bus,
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pc: 0,
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gpr: [0; 15],
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pipeline: [0; 2],
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next_fetch_access: MemoryAccess::NonSeq,
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cpsr,
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spsr: Default::default(),
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banks: Box::new(BankedRegisters::default()),
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bs_carry_out: false,
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#[cfg(feature = "debugger")]
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last_executed: None,
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#[cfg(feature = "debugger")]
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gpr_previous: [0; 15],
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#[cfg(feature = "debugger")]
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breakpoints: Vec::new(),
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#[cfg(feature = "debugger")]
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verbose: false,
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#[cfg(feature = "debugger")]
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trace_opcodes: false,
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#[cfg(feature = "debugger")]
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trace_exceptions: false,
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}
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}
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pub fn weak_ptr(&mut self) -> WeakPointer<Core<I>> {
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WeakPointer::new(self as *mut Core<I>)
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}
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pub fn from_saved_state(bus: Shared<I>, state: SavedCpuState) -> Core<I> {
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Core {
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bus,
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pc: state.pc,
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cpsr: state.cpsr,
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gpr: state.gpr,
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banks: state.banks,
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spsr: state.spsr,
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bs_carry_out: state.bs_carry_out,
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pipeline: state.pipeline,
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next_fetch_access: state.next_fetch_access,
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// savestate does not keep debugger related information, so just reinitialize to default
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#[cfg(feature = "debugger")]
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last_executed: None,
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#[cfg(feature = "debugger")]
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gpr_previous: [0; 15],
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#[cfg(feature = "debugger")]
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breakpoints: Vec::new(),
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#[cfg(feature = "debugger")]
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verbose: false,
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#[cfg(feature = "debugger")]
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trace_opcodes: false,
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#[cfg(feature = "debugger")]
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trace_exceptions: false,
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}
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}
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pub fn save_state(&self) -> SavedCpuState {
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SavedCpuState {
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cpsr: self.cpsr,
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pc: self.pc,
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gpr: self.gpr.clone(),
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spsr: self.spsr,
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banks: self.banks.clone(),
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bs_carry_out: self.bs_carry_out,
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pipeline: self.pipeline.clone(),
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next_fetch_access: self.next_fetch_access,
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}
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}
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pub fn restore_state(&mut self, state: SavedCpuState) {
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self.pc = state.pc;
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self.cpsr = state.cpsr;
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self.gpr = state.gpr;
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self.spsr = state.spsr;
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self.banks = state.banks;
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self.bs_carry_out = state.bs_carry_out;
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self.pipeline = state.pipeline;
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self.next_fetch_access = state.next_fetch_access;
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}
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pub fn set_memory_interface(&mut self, i: Shared<I>) {
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self.bus = i;
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}
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#[cfg(feature = "debugger")]
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pub fn set_verbose(&mut self, v: bool) {
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self.verbose = v;
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}
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pub fn get_reg(&self, r: usize) -> u32 {
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match r {
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0..=14 => self.gpr[r],
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15 => self.pc,
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_ => panic!("invalid register {}", r),
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}
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}
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#[inline]
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/// Gets PC of the currently executed instruction in arm mode
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pub fn pc_arm(&self) -> u32 {
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self.pc.wrapping_sub(8)
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}
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#[inline]
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/// Gets PC of the currently executed instruction in thumb mode
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pub fn pc_thumb(&self) -> u32 {
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self.pc.wrapping_sub(4)
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}
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pub fn get_reg_user(&mut self, r: usize) -> u32 {
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match r {
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0..=7 => self.gpr[r],
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8..=12 => {
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if self.cpsr.mode() == CpuMode::Fiq {
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self.gpr[r]
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} else {
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self.banks.gpr_banked_old_r8_12[r - 8]
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}
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}
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13 => self.banks.gpr_banked_r13[0],
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14 => self.banks.gpr_banked_r14[0],
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_ => panic!("invalid register"),
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}
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}
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pub fn set_reg(&mut self, r: usize, val: u32) {
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match r {
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0..=14 => self.gpr[r] = val,
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15 => {
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self.pc = {
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match self.cpsr.state() {
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CpuState::THUMB => val & !1,
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CpuState::ARM => val & !3,
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}
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}
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}
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_ => panic!("invalid register"),
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}
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}
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pub fn set_reg_user(&mut self, r: usize, val: u32) {
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match r {
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0..=7 => self.gpr[r] = val,
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8..=12 => {
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if self.cpsr.mode() == CpuMode::Fiq {
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self.gpr[r] = val;
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} else {
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self.banks.gpr_banked_old_r8_12[r - 8] = val;
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}
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}
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13 => {
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self.banks.gpr_banked_r13[0] = val;
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}
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14 => {
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self.banks.gpr_banked_r14[0] = val;
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}
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_ => panic!("invalid register"),
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}
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}
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pub fn get_registers(&self) -> [u32; 15] {
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self.gpr.clone()
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}
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pub(super) fn change_mode(&mut self, old_mode: CpuMode, new_mode: CpuMode) {
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let new_index = new_mode.bank_index();
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let old_index = old_mode.bank_index();
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if new_index == old_index {
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return;
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}
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let banks = &mut self.banks;
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banks.spsr_bank[old_index] = self.spsr;
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banks.gpr_banked_r13[old_index] = self.gpr[13];
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banks.gpr_banked_r14[old_index] = self.gpr[14];
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self.spsr = banks.spsr_bank[new_index];
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self.gpr[13] = banks.gpr_banked_r13[new_index];
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self.gpr[14] = banks.gpr_banked_r14[new_index];
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if new_mode == CpuMode::Fiq {
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for r in 0..5 {
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banks.gpr_banked_old_r8_12[r] = self.gpr[r + 8];
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self.gpr[r + 8] = banks.gpr_banked_fiq_r8_12[r];
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}
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} else if old_mode == CpuMode::Fiq {
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for r in 0..5 {
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banks.gpr_banked_fiq_r8_12[r] = self.gpr[r + 8];
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self.gpr[r + 8] = banks.gpr_banked_old_r8_12[r];
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}
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}
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self.cpsr.set_mode(new_mode);
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}
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/// Resets the cpu
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pub fn reset(&mut self) {
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self.exception(Exception::Reset, 0);
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}
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pub fn word_size(&self) -> usize {
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match self.cpsr.state() {
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CpuState::ARM => 4,
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CpuState::THUMB => 2,
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}
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}
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pub(super) fn get_required_multipiler_array_cycles(&self, rs: u32) -> usize {
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if rs & 0xff == rs {
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1
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} else if rs & 0xffff == rs {
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2
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} else if rs & 0xffffff == rs {
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3
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} else {
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4
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}
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}
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#[inline]
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pub(super) fn check_arm_cond(&self, cond: ArmCond) -> bool {
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use ArmCond::*;
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match cond {
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Invalid => {
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// TODO - we would normally want to panic here
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false
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}
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EQ => self.cpsr.Z(),
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NE => !self.cpsr.Z(),
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HS => self.cpsr.C(),
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LO => !self.cpsr.C(),
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MI => self.cpsr.N(),
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PL => !self.cpsr.N(),
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VS => self.cpsr.V(),
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VC => !self.cpsr.V(),
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HI => self.cpsr.C() && !self.cpsr.Z(),
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LS => !self.cpsr.C() || self.cpsr.Z(),
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GE => self.cpsr.N() == self.cpsr.V(),
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LT => self.cpsr.N() != self.cpsr.V(),
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GT => !self.cpsr.Z() && (self.cpsr.N() == self.cpsr.V()),
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LE => self.cpsr.Z() || (self.cpsr.N() != self.cpsr.V()),
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AL => true,
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}
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}
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#[cfg(feature = "debugger")]
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fn debugger_record_step(&mut self, d: DecodedInstruction) {
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self.gpr_previous = self.get_registers();
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self.last_executed = Some(d);
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}
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cfg_if! {
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if #[cfg(feature = "arm7tdmi_dispatch_table")] {
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fn step_arm_exec(&mut self, insn: u32) -> CpuAction {
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let hash = (((insn >> 16) & 0xff0) | ((insn >> 4) & 0x00f)) as usize;
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let arm_info = &Self::ARM_LUT[hash];
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#[cfg(feature = "debugger")]
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self.debugger_record_step(DecodedInstruction::Arm(ArmInstruction::new(
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insn,
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self.pc.wrapping_sub(8),
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arm_info.fmt,
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)));
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(arm_info.handler_fn)(self, insn)
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}
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fn step_thumb_exec(&mut self, insn: u16) -> CpuAction {
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let thumb_info = &Self::THUMB_LUT[(insn >> 6) as usize];
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#[cfg(feature = "debugger")]
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self.debugger_record_step(DecodedInstruction::Thumb(ThumbInstruction::new(
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insn,
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self.pc.wrapping_sub(4),
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thumb_info.fmt,
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)));
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(thumb_info.handler_fn)(self, insn)
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}
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} else {
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fn step_arm_exec(&mut self, insn: u32) -> CpuAction {
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let arm_fmt = ArmFormat::from(insn);
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#[cfg(feature = "debugger")]
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self.debugger_record_step(DecodedInstruction::Arm(ArmInstruction::new(
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insn,
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self.pc.wrapping_sub(8),
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arm_fmt,
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)));
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self.exec_arm(insn, arm_fmt)
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}
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fn step_thumb_exec(&mut self, insn: u16) -> CpuAction {
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let thumb_fmt = ThumbFormat::from(insn);
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#[cfg(feature = "debugger")]
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self.debugger_record_step(DecodedInstruction::Thumb(ThumbInstruction::new(
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insn,
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self.pc.wrapping_sub(4),
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thumb_fmt,
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)));
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self.exec_thumb(insn, thumb_fmt)
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}
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}
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}
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/// 2S + 1N
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#[inline(always)]
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pub fn reload_pipeline16(&mut self) {
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self.pipeline[0] = self.load_16(self.pc, NonSeq) as u32;
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self.advance_thumb();
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self.pipeline[1] = self.load_16(self.pc, Seq) as u32;
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self.advance_thumb();
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self.next_fetch_access = Seq;
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}
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/// 2S + 1N
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#[inline(always)]
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pub fn reload_pipeline32(&mut self) {
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self.pipeline[0] = self.load_32(self.pc, NonSeq);
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self.advance_arm();
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self.pipeline[1] = self.load_32(self.pc, Seq);
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self.advance_arm();
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self.next_fetch_access = Seq;
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}
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#[inline]
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pub(super) fn advance_thumb(&mut self) {
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self.pc = self.pc.wrapping_add(2)
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}
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#[inline]
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pub(super) fn advance_arm(&mut self) {
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self.pc = self.pc.wrapping_add(4)
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}
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#[inline]
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pub fn get_decoded_opcode(&self) -> u32 {
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self.pipeline[0]
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}
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#[inline]
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pub fn get_prefetched_opcode(&self) -> u32 {
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self.pipeline[1]
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}
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/// Perform a pipeline step
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/// If an instruction was executed in this step, return it.
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pub fn step(&mut self) {
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match self.cpsr.state() {
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CpuState::ARM => {
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let pc = self.pc & !3;
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let fetched_now = self.load_32(pc, self.next_fetch_access);
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let insn = self.pipeline[0];
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self.pipeline[0] = self.pipeline[1];
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self.pipeline[1] = fetched_now;
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let cond = ArmCond::from_u8(insn.bit_range(28..32) as u8)
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.unwrap_or_else(|| unsafe { std::hint::unreachable_unchecked() });
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if cond != ArmCond::AL {
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if !self.check_arm_cond(cond) {
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self.advance_arm();
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self.next_fetch_access = MemoryAccess::NonSeq;
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return;
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}
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}
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match self.step_arm_exec(insn) {
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CpuAction::AdvancePC(access) => {
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self.next_fetch_access = access;
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self.advance_arm();
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}
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CpuAction::PipelineFlushed => {}
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}
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}
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CpuState::THUMB => {
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let pc = self.pc & !1;
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let fetched_now = self.load_16(pc, self.next_fetch_access);
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let insn = self.pipeline[0];
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self.pipeline[0] = self.pipeline[1];
|
|
self.pipeline[1] = fetched_now as u32;
|
|
match self.step_thumb_exec(insn as u16) {
|
|
CpuAction::AdvancePC(access) => {
|
|
self.advance_thumb();
|
|
self.next_fetch_access = access;
|
|
}
|
|
CpuAction::PipelineFlushed => {}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
/// Get's the address of the next instruction that is going to be executed
|
|
pub fn get_next_pc(&self) -> Addr {
|
|
let insn_size = self.word_size() as u32;
|
|
self.pc - 2 * insn_size
|
|
}
|
|
|
|
pub fn get_cpu_state(&self) -> CpuState {
|
|
self.cpsr.state()
|
|
}
|
|
|
|
pub fn skip_bios(&mut self) {
|
|
self.banks.gpr_banked_r13[0] = 0x0300_7f00; // USR/SYS
|
|
self.banks.gpr_banked_r13[1] = 0x0300_7f00; // FIQ
|
|
self.banks.gpr_banked_r13[2] = 0x0300_7fa0; // IRQ
|
|
self.banks.gpr_banked_r13[3] = 0x0300_7fe0; // SVC
|
|
self.banks.gpr_banked_r13[4] = 0x0300_7f00; // ABT
|
|
self.banks.gpr_banked_r13[5] = 0x0300_7f00; // UND
|
|
|
|
self.gpr[13] = 0x0300_7f00;
|
|
self.pc = 0x0800_0000;
|
|
|
|
self.cpsr.set(0x5f);
|
|
}
|
|
}
|
|
|
|
#[cfg(feature = "debugger")]
|
|
impl<I: MemoryInterface> fmt::Display for Core<I> {
|
|
fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
|
|
writeln!(f, "ARM7TDMI Core Status:")?;
|
|
writeln!(f, "\tCPSR: {}", self.cpsr)?;
|
|
writeln!(f, "\tGeneral Purpose Registers:")?;
|
|
let reg_normal_style = Style::new().bold();
|
|
let reg_dirty_style = Colour::Black.bold().on(Colour::Yellow);
|
|
let gpr = self.get_registers();
|
|
for i in 0..15 {
|
|
let mut reg_name = reg_string(i).to_string();
|
|
reg_name.make_ascii_uppercase();
|
|
|
|
let style = if gpr[i] != self.gpr_previous[i] {
|
|
®_dirty_style
|
|
} else {
|
|
®_normal_style
|
|
};
|
|
|
|
let entry = format!("\t{:-3} = 0x{:08x}", reg_name, gpr[i]);
|
|
|
|
write!(
|
|
f,
|
|
"{}{}",
|
|
style.paint(entry),
|
|
if (i + 1) % 4 == 0 { "\n" } else { "" }
|
|
)?;
|
|
}
|
|
let pc = format!("\tPC = 0x{:08x}", self.get_next_pc());
|
|
writeln!(f, "{}", reg_normal_style.paint(pc))
|
|
}
|
|
}
|
|
|
|
#[cfg(feature = "arm7tdmi_dispatch_table")]
|
|
include!(concat!(env!("OUT_DIR"), "/arm_lut.rs"));
|
|
#[cfg(feature = "arm7tdmi_dispatch_table")]
|
|
include!(concat!(env!("OUT_DIR"), "/thumb_lut.rs"));
|