b03fe3567e
Ran cargo-fix to automatically fix most of the build warnings, Cleaned up dead code, and fix the rest manually Former-commit-id: f35faba46b40eaf9c047efb8ab1e77ffa24d41b6
686 lines
22 KiB
Rust
686 lines
22 KiB
Rust
use crate::bit::BitIndex;
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use super::super::alu::*;
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use crate::core::arm7tdmi::psr::RegPSR;
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use crate::core::arm7tdmi::CpuAction;
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use crate::core::arm7tdmi::{Addr, Core, CpuMode, CpuState, REG_LR, REG_PC};
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use crate::core::sysbus::SysBus;
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use crate::core::Bus;
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use super::*;
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impl Core {
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pub fn exec_arm(&mut self, bus: &mut SysBus, insn: ArmInstruction) -> CpuAction {
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if !self.check_arm_cond(insn.cond) {
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self.S_cycle32(bus, self.pc);
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return CpuAction::AdvancePC;
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}
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match insn.fmt {
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ArmFormat::BX => self.exec_bx(bus, insn),
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ArmFormat::B_BL => self.exec_b_bl(bus, insn),
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ArmFormat::DP => self.exec_data_processing(bus, insn),
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ArmFormat::SWI => {
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self.software_interrupt(bus, self.pc - 4, insn.swi_comment());
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CpuAction::FlushPipeline
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}
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ArmFormat::LDR_STR => self.exec_ldr_str(bus, insn),
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ArmFormat::LDR_STR_HS_IMM => self.exec_ldr_str_hs(bus, insn),
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ArmFormat::LDR_STR_HS_REG => self.exec_ldr_str_hs(bus, insn),
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ArmFormat::LDM_STM => self.exec_ldm_stm(bus, insn),
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ArmFormat::MRS => self.move_from_status_register(bus, insn.rd(), insn.spsr_flag()),
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ArmFormat::MSR_REG => self.exec_msr_reg(bus, insn),
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ArmFormat::MSR_FLAGS => self.exec_msr_flags(bus, insn),
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ArmFormat::MUL_MLA => self.exec_mul_mla(bus, insn),
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ArmFormat::MULL_MLAL => self.exec_mull_mlal(bus, insn),
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ArmFormat::SWP => self.exec_arm_swp(bus, insn),
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}
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}
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/// Cycles 2S+1N
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fn exec_b_bl(&mut self, sb: &mut SysBus, insn: ArmInstruction) -> CpuAction {
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self.S_cycle32(sb, self.pc);
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if insn.link_flag() {
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self.set_reg(REG_LR, (insn.pc + (self.word_size() as u32)) & !0b1);
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}
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self.pc = (self.pc as i32).wrapping_add(insn.branch_offset()) as u32 & !1;
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self.reload_pipeline32(sb);
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CpuAction::FlushPipeline
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}
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pub fn branch_exchange(&mut self, sb: &mut SysBus, mut addr: Addr) -> CpuAction {
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match self.cpsr.state() {
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CpuState::ARM => self.S_cycle32(sb, self.pc),
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CpuState::THUMB => self.S_cycle16(sb, self.pc),
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}
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if addr.bit(0) {
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addr = addr & !0x1;
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self.cpsr.set_state(CpuState::THUMB);
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self.pc = addr;
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self.reload_pipeline16(sb);
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} else {
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addr = addr & !0x3;
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self.cpsr.set_state(CpuState::ARM);
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self.pc = addr;
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self.reload_pipeline32(sb);
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}
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CpuAction::FlushPipeline
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}
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/// Cycles 2S+1N
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fn exec_bx(&mut self, sb: &mut SysBus, insn: ArmInstruction) -> CpuAction {
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self.branch_exchange(sb, self.get_reg(insn.rn()))
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}
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fn move_from_status_register(
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&mut self,
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sb: &mut SysBus,
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rd: usize,
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is_spsr: bool,
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) -> CpuAction {
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let result = if is_spsr {
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self.spsr.get()
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} else {
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self.cpsr.get()
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};
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self.set_reg(rd, result);
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self.S_cycle32(sb, self.pc);
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CpuAction::AdvancePC
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}
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fn exec_msr_reg(&mut self, sb: &mut SysBus, insn: ArmInstruction) -> CpuAction {
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self.write_status_register(sb, insn.spsr_flag(), self.get_reg(insn.rm()))
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}
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fn write_status_register(&mut self, sb: &mut SysBus, is_spsr: bool, value: u32) -> CpuAction {
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let new_status_reg = RegPSR::new(value);
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match self.cpsr.mode() {
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CpuMode::User => {
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if is_spsr {
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panic!("User mode can't access SPSR")
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}
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self.cpsr.set_flag_bits(value);
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}
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_ => {
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if is_spsr {
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self.spsr.set(value);
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} else {
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let t_bit = self.cpsr.state();
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let old_mode = self.cpsr.mode();
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self.cpsr.set(value);
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if t_bit != self.cpsr.state() {
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panic!("T bit changed from MSR");
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}
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let new_mode = new_status_reg.mode();
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if old_mode != new_mode {
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self.change_mode(old_mode, new_mode);
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}
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}
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}
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}
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self.S_cycle32(sb, self.pc);
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CpuAction::AdvancePC
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}
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fn exec_msr_flags(&mut self, sb: &mut SysBus, insn: ArmInstruction) -> CpuAction {
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self.S_cycle32(sb, self.pc);
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let op = insn.operand2();
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let op = self.decode_operand2(op);
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if insn.spsr_flag() {
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self.spsr.set_flag_bits(op);
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} else {
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self.cpsr.set_flag_bits(op);
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}
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CpuAction::AdvancePC
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}
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fn decode_operand2(&mut self, op2: BarrelShifterValue) -> u32 {
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match op2 {
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BarrelShifterValue::RotatedImmediate(val, amount) => {
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self.ror(val, amount, self.cpsr.C(), false, true)
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}
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BarrelShifterValue::ShiftedRegister(x) => self.register_shift(x),
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_ => unreachable!(),
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}
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}
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fn transfer_spsr_mode(&mut self) {
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let spsr = self.spsr;
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if self.cpsr.mode() != spsr.mode() {
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self.change_mode(self.cpsr.mode(), spsr.mode());
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}
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self.cpsr = spsr;
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}
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/// Logical/Arithmetic ALU operations
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///
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/// Cycles: 1S+x+y (from GBATEK)
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/// Add x=1I cycles if Op2 shifted-by-register. Add y=1S+1N cycles if Rd=R15.
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fn exec_data_processing(&mut self, sb: &mut SysBus, insn: ArmInstruction) -> CpuAction {
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use AluOpCode::*;
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self.S_cycle32(sb, self.pc);
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let mut op1 = if insn.rn() == REG_PC {
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insn.pc + 8
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} else {
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self.get_reg(insn.rn())
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};
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let mut s_flag = insn.set_cond_flag();
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let opcode = insn.opcode().unwrap();
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let op2 = insn.operand2();
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match op2 {
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BarrelShifterValue::ShiftedRegister(shifted_reg) => {
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if insn.rn() == REG_PC && shifted_reg.is_shifted_by_reg() {
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op1 += 4;
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}
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}
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_ => {}
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}
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let op2 = self.decode_operand2(op2);
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let reg_rd = insn.rd();
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if !s_flag {
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match opcode {
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TEQ => {
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return self.write_status_register(sb, false, op2);
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}
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CMN => {
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return self.write_status_register(sb, true, op2);
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}
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TST => return self.move_from_status_register(sb, reg_rd, false),
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CMP => return self.move_from_status_register(sb, reg_rd, true),
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_ => (),
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}
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}
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if reg_rd == REG_PC && s_flag {
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self.transfer_spsr_mode();
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s_flag = false;
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}
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let carry = self.cpsr.C() as u32;
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let alu_res = if s_flag {
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let mut carry = self.bs_carry_out;
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let mut overflow = self.cpsr.V();
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let result = match opcode {
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AND | TST => op1 & op2,
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EOR | TEQ => op1 ^ op2,
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SUB | CMP => self.alu_sub_flags(op1, op2, &mut carry, &mut overflow),
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RSB => self.alu_sub_flags(op2, op1, &mut carry, &mut overflow),
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ADD | CMN => self.alu_add_flags(op1, op2, &mut carry, &mut overflow),
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ADC => self.alu_adc_flags(op1, op2, &mut carry, &mut overflow),
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SBC => self.alu_sbc_flags(op1, op2, &mut carry, &mut overflow),
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RSC => self.alu_sbc_flags(op2, op1, &mut carry, &mut overflow),
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ORR => op1 | op2,
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MOV => op2,
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BIC => op1 & (!op2),
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MVN => !op2,
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};
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self.alu_update_flags(result, opcode.is_arithmetic(), carry, overflow);
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if opcode.is_setting_flags() {
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None
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} else {
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Some(result)
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}
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} else {
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Some(match opcode {
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AND => op1 & op2,
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EOR => op1 ^ op2,
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SUB => op1.wrapping_sub(op2),
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RSB => op2.wrapping_sub(op1),
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ADD => op1.wrapping_add(op2),
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ADC => op1.wrapping_add(op2).wrapping_add(carry),
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SBC => op1.wrapping_sub(op2.wrapping_add(1 - carry)),
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RSC => op2.wrapping_sub(op1.wrapping_add(1 - carry)),
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ORR => op1 | op2,
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MOV => op2,
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BIC => op1 & (!op2),
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MVN => !op2,
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_ => panic!("{} should be a PSR transfer", opcode),
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})
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};
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let mut result = CpuAction::AdvancePC;
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if let Some(alu_res) = alu_res {
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self.set_reg(reg_rd, alu_res as u32);
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if reg_rd == REG_PC {
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// T bit might have changed
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match self.cpsr.state() {
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CpuState::ARM => self.reload_pipeline32(sb),
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CpuState::THUMB => self.reload_pipeline16(sb),
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};
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result = CpuAction::FlushPipeline;
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}
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}
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result
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}
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/// Memory Load/Store
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/// Instruction | Cycles | Flags | Expl.
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/// ------------------------------------------------------------------------------
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/// LDR{cond}{B}{T} Rd,<Address> | 1S+1N+1I+y | ---- | Rd=[Rn+/-<offset>]
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/// STR{cond}{B}{T} Rd,<Address> | 2N | ---- | [Rn+/-<offset>]=Rd
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/// ------------------------------------------------------------------------------
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/// For LDR, add y=1S+1N if Rd=R15.
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fn exec_ldr_str(&mut self, sb: &mut SysBus, insn: ArmInstruction) -> CpuAction {
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let mut result = CpuAction::AdvancePC;
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let load = insn.load_flag();
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let pre_index = insn.pre_index_flag();
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let writeback = insn.write_back_flag();
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let base_reg = insn.rn();
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let dest_reg = insn.rd();
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let mut addr = self.get_reg(base_reg);
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if base_reg == REG_PC {
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addr = insn.pc + 8; // prefetching
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}
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let offset = self.get_barrel_shifted_value(insn.ldr_str_offset());
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let effective_addr = (addr as i32).wrapping_add(offset as i32) as Addr;
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// TODO - confirm this
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let old_mode = self.cpsr.mode();
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if !pre_index && writeback {
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self.change_mode(old_mode, CpuMode::User);
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}
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addr = if insn.pre_index_flag() {
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effective_addr
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} else {
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addr
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};
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if load {
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self.S_cycle32(sb, self.pc);
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let data = if insn.transfer_size() == 1 {
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self.N_cycle8(sb, addr);
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sb.read_8(addr) as u32
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} else {
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self.N_cycle32(sb, addr);
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self.ldr_word(addr, sb)
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};
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self.set_reg(dest_reg, data);
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// +1I
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self.add_cycle();
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if dest_reg == REG_PC {
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self.reload_pipeline32(sb);
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result = CpuAction::FlushPipeline;
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}
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} else {
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let value = if dest_reg == REG_PC {
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insn.pc + 12
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} else {
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self.get_reg(dest_reg)
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};
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if insn.transfer_size() == 1 {
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self.N_cycle8(sb, addr);
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self.write_8(addr, value as u8, sb);
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} else {
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self.N_cycle32(sb, addr);
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self.write_32(addr & !0x3, value, sb);
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};
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self.N_cycle32(sb, self.pc);
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}
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if !load || base_reg != dest_reg {
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if !pre_index {
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self.set_reg(base_reg, effective_addr);
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} else if insn.write_back_flag() {
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self.set_reg(base_reg, effective_addr);
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}
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}
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if !pre_index && insn.write_back_flag() {
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self.change_mode(self.cpsr.mode(), old_mode);
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}
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result
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}
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fn exec_ldr_str_hs(&mut self, sb: &mut SysBus, insn: ArmInstruction) -> CpuAction {
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let mut result = CpuAction::AdvancePC;
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let load = insn.load_flag();
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let pre_index = insn.pre_index_flag();
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let writeback = insn.write_back_flag();
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let base_reg = insn.rn();
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let dest_reg = insn.rd();
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let mut addr = self.get_reg(base_reg);
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if base_reg == REG_PC {
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addr = insn.pc + 8; // prefetching
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}
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let offset = self.get_barrel_shifted_value(insn.ldr_str_hs_offset().unwrap());
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// TODO - confirm this
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let old_mode = self.cpsr.mode();
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if !pre_index && writeback {
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self.change_mode(old_mode, CpuMode::User);
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}
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let effective_addr = (addr as i32).wrapping_add(offset as i32) as Addr;
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addr = if insn.pre_index_flag() {
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effective_addr
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} else {
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addr
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};
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if load {
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self.S_cycle32(sb, self.pc);
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let data = match insn.halfword_data_transfer_type().unwrap() {
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ArmHalfwordTransferType::SignedByte => {
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self.N_cycle8(sb, addr);
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sb.read_8(addr) as u8 as i8 as u32
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}
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ArmHalfwordTransferType::SignedHalfwords => {
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self.N_cycle16(sb, addr);
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self.ldr_sign_half(addr, sb)
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}
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ArmHalfwordTransferType::UnsignedHalfwords => {
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self.N_cycle16(sb, addr);
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self.ldr_half(addr, sb)
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}
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};
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self.set_reg(dest_reg, data);
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// +1I
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self.add_cycle();
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if dest_reg == REG_PC {
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self.reload_pipeline32(sb);
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result = CpuAction::FlushPipeline;
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}
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} else {
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let value = if dest_reg == REG_PC {
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insn.pc + 12
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} else {
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self.get_reg(dest_reg)
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};
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match insn.halfword_data_transfer_type().unwrap() {
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ArmHalfwordTransferType::UnsignedHalfwords => {
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self.N_cycle32(sb, addr);
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self.write_16(addr, value as u16, sb);
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self.N_cycle32(sb, self.pc);
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}
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_ => panic!("invalid HS flags for L=0"),
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};
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}
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if !load || base_reg != dest_reg {
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if !pre_index {
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self.set_reg(base_reg, effective_addr);
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} else if insn.write_back_flag() {
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self.set_reg(base_reg, effective_addr);
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}
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}
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result
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}
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fn exec_ldm_stm(&mut self, sb: &mut SysBus, insn: ArmInstruction) -> CpuAction {
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let mut result = CpuAction::AdvancePC;
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let mut full = insn.pre_index_flag();
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let ascending = insn.add_offset_flag();
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let s_flag = insn.raw.bit(22);
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let is_load = insn.load_flag();
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let mut writeback = insn.write_back_flag();
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let base_reg = insn.rn();
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let mut base_addr = self.get_reg(base_reg);
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let rlist = insn.register_list();
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if s_flag {
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match self.cpsr.mode() {
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CpuMode::User | CpuMode::System => {
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panic!("LDM/STM with S bit in unprivileged mode")
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}
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_ => {}
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};
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}
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let user_bank_transfer = if s_flag {
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if is_load {
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!rlist.bit(REG_PC)
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} else {
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true
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}
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} else {
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false
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};
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let old_mode = self.cpsr.mode();
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if user_bank_transfer {
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self.change_mode(old_mode, CpuMode::User);
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}
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let psr_transfer = s_flag & is_load & rlist.bit(REG_PC);
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let rlist_count = rlist.count_ones();
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let old_base = base_addr;
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if rlist != 0 && !ascending {
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base_addr = base_addr.wrapping_sub(rlist_count * 4);
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if writeback {
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self.set_reg(base_reg, base_addr);
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writeback = false;
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}
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full = !full;
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}
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let mut addr = base_addr;
|
|
|
|
if rlist != 0 {
|
|
if is_load {
|
|
self.add_cycle();
|
|
self.N_cycle32(sb, self.pc);
|
|
for r in 0..16 {
|
|
if rlist.bit(r) {
|
|
if r == base_reg {
|
|
writeback = false;
|
|
}
|
|
if full {
|
|
addr = addr.wrapping_add(4);
|
|
}
|
|
|
|
let val = sb.read_32(addr);
|
|
self.S_cycle32(sb, self.pc);
|
|
|
|
self.set_reg(r, val);
|
|
|
|
if r == REG_PC {
|
|
if psr_transfer {
|
|
self.transfer_spsr_mode();
|
|
}
|
|
self.reload_pipeline32(sb);
|
|
result = CpuAction::FlushPipeline;
|
|
}
|
|
|
|
if !full {
|
|
addr = addr.wrapping_add(4);
|
|
}
|
|
}
|
|
}
|
|
} else {
|
|
let mut first = true;
|
|
for r in 0..16 {
|
|
if rlist.bit(r) {
|
|
let val = if r != base_reg {
|
|
if r == REG_PC {
|
|
insn.pc + 12
|
|
} else {
|
|
self.get_reg(r)
|
|
}
|
|
} else {
|
|
if first {
|
|
old_base
|
|
} else {
|
|
let x = rlist_count * 4;
|
|
if ascending {
|
|
old_base + x
|
|
} else {
|
|
old_base - x
|
|
}
|
|
}
|
|
};
|
|
|
|
if full {
|
|
addr = addr.wrapping_add(4);
|
|
}
|
|
|
|
if first {
|
|
self.N_cycle32(sb, addr);
|
|
first = false;
|
|
} else {
|
|
self.S_cycle32(sb, addr);
|
|
}
|
|
self.write_32(addr, val, sb);
|
|
|
|
if !full {
|
|
addr = addr.wrapping_add(4);
|
|
}
|
|
}
|
|
}
|
|
self.N_cycle32(sb, self.pc);
|
|
}
|
|
} else {
|
|
if is_load {
|
|
let val = self.ldr_word(addr, sb);
|
|
self.set_reg(REG_PC, val & !3);
|
|
self.reload_pipeline32(sb);
|
|
result = CpuAction::FlushPipeline;
|
|
} else {
|
|
self.write_32(addr, self.pc + 4, sb);
|
|
}
|
|
addr = addr.wrapping_add(0x40);
|
|
}
|
|
|
|
if user_bank_transfer {
|
|
self.change_mode(self.cpsr.mode(), old_mode);
|
|
}
|
|
|
|
if writeback {
|
|
self.set_reg(base_reg, addr as u32);
|
|
}
|
|
|
|
result
|
|
}
|
|
|
|
fn exec_mul_mla(&mut self, sb: &mut SysBus, insn: ArmInstruction) -> CpuAction {
|
|
let (rd, rn, rs, rm) = (insn.rd(), insn.rn(), insn.rs(), insn.rm());
|
|
|
|
// check validity
|
|
assert!(!(REG_PC == rd || REG_PC == rn || REG_PC == rs || REG_PC == rm));
|
|
assert!(rd != rm);
|
|
|
|
let op1 = self.get_reg(rm);
|
|
let op2 = self.get_reg(rs);
|
|
let mut result = op1.wrapping_mul(op2);
|
|
|
|
if insn.accumulate_flag() {
|
|
result = result.wrapping_add(self.get_reg(rn));
|
|
self.add_cycle();
|
|
}
|
|
|
|
self.set_reg(rd, result);
|
|
|
|
let m = self.get_required_multipiler_array_cycles(op2);
|
|
for _ in 0..m {
|
|
self.add_cycle();
|
|
}
|
|
|
|
if insn.set_cond_flag() {
|
|
self.cpsr.set_N((result as i32) < 0);
|
|
self.cpsr.set_Z(result == 0);
|
|
self.cpsr.set_C(false);
|
|
self.cpsr.set_V(false);
|
|
}
|
|
|
|
self.S_cycle32(sb, self.pc);
|
|
|
|
CpuAction::AdvancePC
|
|
}
|
|
|
|
fn exec_mull_mlal(&mut self, sb: &mut SysBus, insn: ArmInstruction) -> CpuAction {
|
|
let (rd_hi, rd_lo, rn, rs, rm) =
|
|
(insn.rd_hi(), insn.rd_lo(), insn.rn(), insn.rs(), insn.rm());
|
|
|
|
// check validity
|
|
assert!(
|
|
!(REG_PC == rd_hi || REG_PC == rd_lo || REG_PC == rn || REG_PC == rs || REG_PC == rm)
|
|
);
|
|
assert!(!(rd_hi != rd_hi && rd_hi != rm && rd_lo != rm));
|
|
|
|
let op1 = self.get_reg(rm);
|
|
let op2 = self.get_reg(rs);
|
|
let mut result: u64 = if insn.u_flag() {
|
|
// signed
|
|
(op1 as i32 as i64).wrapping_mul(op2 as i32 as i64) as u64
|
|
} else {
|
|
(op1 as u64).wrapping_mul(op2 as u64)
|
|
};
|
|
self.add_cycle();
|
|
|
|
if insn.accumulate_flag() {
|
|
let hi = self.get_reg(rd_hi) as u64;
|
|
let lo = self.get_reg(rd_lo) as u64;
|
|
result = result.wrapping_add(hi << 32 | lo);
|
|
self.add_cycle();
|
|
}
|
|
|
|
self.set_reg(rd_hi, (result >> 32) as i32 as u32);
|
|
self.set_reg(rd_lo, (result & 0xffffffff) as i32 as u32);
|
|
|
|
let m = self.get_required_multipiler_array_cycles(self.get_reg(rs));
|
|
for _ in 0..m {
|
|
self.add_cycle();
|
|
}
|
|
|
|
if insn.set_cond_flag() {
|
|
self.cpsr.set_N(result.bit(63));
|
|
self.cpsr.set_Z(result == 0);
|
|
self.cpsr.set_C(false);
|
|
self.cpsr.set_V(false);
|
|
}
|
|
|
|
self.S_cycle32(sb, self.pc);
|
|
|
|
CpuAction::AdvancePC
|
|
}
|
|
|
|
fn exec_arm_swp(&mut self, sb: &mut SysBus, insn: ArmInstruction) -> CpuAction {
|
|
let base_addr = self.get_reg(insn.rn());
|
|
if insn.transfer_size() == 1 {
|
|
let t = sb.read_8(base_addr);
|
|
self.N_cycle8(sb, base_addr);
|
|
sb.write_8(base_addr, self.get_reg(insn.rm()) as u8);
|
|
self.S_cycle8(sb, base_addr);
|
|
self.set_reg(insn.rd(), t as u32);
|
|
} else {
|
|
let t = self.ldr_word(base_addr, sb);
|
|
self.N_cycle32(sb, base_addr);
|
|
self.write_32(base_addr, self.get_reg(insn.rm()), sb);
|
|
self.S_cycle32(sb, base_addr);
|
|
self.set_reg(insn.rd(), t as u32);
|
|
}
|
|
self.add_cycle();
|
|
self.N_cycle32(sb, self.pc);
|
|
|
|
CpuAction::AdvancePC
|
|
}
|
|
}
|