133 lines
3.4 KiB
Rust
133 lines
3.4 KiB
Rust
use std::io;
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use super::arm7tdmi::Addr;
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use super::arm7tdmi::bus::{Bus, MemoryAccess, MemoryAccessType, MemoryAccessWidth};
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use byteorder::{LittleEndian, ReadBytesExt, WriteBytesExt};
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const VIDEO_RAM_SIZE: usize = 128 * 1024;
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const WORK_RAM_SIZE: usize = 256 * 1024;
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const INTERNAL_RAM: usize = 32 * 1024;
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const PALETTE_AM_SIZE: usize = 1 * 1024;
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const OAM_SIZE: usize = 1 * 1024;
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const BIOS_SIZE: usize = 16 * 1024;
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const GAMEPAK_ROM_SIZE: usize = 32 * 1024 * 1024;
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#[derive(Debug)]
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struct BiosROM(Vec<u8>);
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impl Bus for BiosROM {
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fn read_32(&self, addr: Addr) -> u32 {
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let addr = addr as usize;
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(&self.0[addr..addr + 4])
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.read_u32::<LittleEndian>()
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.unwrap()
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}
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fn read_16(&self, addr: Addr) -> u16 {
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let addr = addr as usize;
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(&self.0[addr..addr + 4])
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.read_u16::<LittleEndian>()
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.unwrap()
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}
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fn read_8(&self, addr: Addr) -> u8 {
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self.0[addr as usize]
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}
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fn write_32(&mut self, addr: Addr, value: u32) -> Result<(), io::Error> {
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let mut wrt = io::Cursor::new(&mut self.0);
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wrt.set_position(addr as u64);
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wrt.write_u32::<LittleEndian>(value)
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}
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fn write_16(&mut self, addr: Addr, value: u16) -> Result<(), io::Error> {
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let mut wrt = io::Cursor::new(&mut self.0);
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wrt.set_position(addr as u64);
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wrt.write_u16::<LittleEndian>(value)
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}
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fn write_8(&mut self, addr: Addr, value: u8) -> Result<(), io::Error> {
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let mut wrt = io::Cursor::new(&mut self.0);
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wrt.write_u8(value)
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}
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fn get_bytes(&self, addr: Addr, size: usize) -> Option<&[u8]> {
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let addr = addr as usize;
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if addr + size > self.0.len() {
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None
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} else {
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Some(&self.0[addr..addr + size])
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}
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}
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fn get_cycles(&self, _addr: Addr, _access: MemoryAccess) -> usize {
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1
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}
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}
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#[derive(Debug)]
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enum SysBusDevice {
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BiosROM(BiosROM)
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}
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#[derive(Debug)]
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pub struct SysBus {
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bios: BiosROM
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}
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impl SysBus {
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pub fn new(bios_rom: Vec<u8>) -> SysBus {
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SysBus { bios: BiosROM(bios_rom) }
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}
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fn map(&self, addr: Addr) -> & impl Bus {
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match addr as usize {
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0...BIOS_SIZE => &self.bios,
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_ => panic!("unmapped address")
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}
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}
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fn map_mut(&mut self, addr: Addr) -> &mut impl Bus {
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match addr as usize {
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0...BIOS_SIZE => &mut self.bios,
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_ => panic!("unmapped address")
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}
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}
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}
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impl Bus for SysBus {
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fn read_32(&self, addr: Addr) -> u32 {
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self.map(addr).read_32(addr)
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}
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fn read_16(&self, addr: Addr) -> u16 {
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self.map(addr).read_16(addr)
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}
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fn read_8(&self, addr: Addr) -> u8 {
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self.map(addr).read_8(addr)
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}
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fn write_32(&mut self, addr: Addr, value: u32) -> Result<(), io::Error> {
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self.map_mut(addr).write_32(addr, value)
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}
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fn write_16(&mut self, addr: Addr, value: u16) -> Result<(), io::Error> {
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self.map_mut(addr).write_16(addr, value)
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}
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fn write_8(&mut self, addr: Addr, value: u8) -> Result<(), io::Error> {
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self.map_mut(addr).write_8(addr, value)
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}
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fn get_bytes(&self, addr: Addr, size: usize) -> Option<&[u8]> {
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self.map(addr).get_bytes(addr, size)
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}
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fn get_cycles(&self, addr: Addr, access: MemoryAccess) -> usize {
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self.map(addr).get_cycles(addr, access)
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}
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}
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