Impl Thumb LdrStrSp
Untested. Former-commit-id: 8fa842d4969e30247fc1706dfe053c7dfbb37843
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@ -74,6 +74,16 @@ impl ThumbInstruction {
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)
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}
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fn fmt_thumb_ldr_str_sp(&self, f: &mut fmt::Formatter) -> fmt::Result {
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write!(
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f,
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"{op}\t{Rd}, [sp, #{Imm:#x}]",
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op = if self.is_load() { "ldr" } else { "str" },
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Rd = reg_string(self.rd()),
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Imm = self.word8(),
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)
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}
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fn fmt_thumb_add_sub(&self, f: &mut fmt::Formatter) -> fmt::Result {
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let operand = if self.is_immediate_operand() {
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format!("#{:x}", self.raw.bit_range(6..9))
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@ -140,6 +150,7 @@ impl fmt::Display for ThumbInstruction {
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ThumbFormat::HiRegOpOrBranchExchange => self.fmt_thumb_high_reg_op_or_bx(f),
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ThumbFormat::LdrPc => self.fmt_thumb_ldr_pc(f),
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ThumbFormat::LdrStrRegOffset => self.fmt_thumb_ldr_str_reg_offset(f),
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ThumbFormat::LdrStrSp => self.fmt_thumb_ldr_str_sp(f),
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ThumbFormat::AddSp => self.fmt_thumb_add_sp(f),
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ThumbFormat::PushPop => self.fmt_thumb_push_pop(f),
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ThumbFormat::BranchConditional => self.fmt_thumb_branch_with_cond(f),
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@ -129,6 +129,19 @@ impl Core {
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Ok(CpuPipelineAction::IncPC)
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}
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fn exec_thumb_ldr_str_sp(&mut self, bus: &mut Bus, insn: ThumbInstruction) -> CpuExecResult {
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let addr = (self.gpr[REG_SP] & !0b10) + 4 + (insn.word8() as Addr);
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if insn.is_load() {
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let data = self.load_32(addr, bus);
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self.add_cycle();
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self.gpr[insn.rd()] = data;
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} else {
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self.store_32(addr, self.gpr[insn.rd()], bus);
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}
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Ok(CpuPipelineAction::IncPC)
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}
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fn exec_thumb_add_sp(&mut self, bus: &mut Bus, insn: ThumbInstruction) -> CpuExecResult {
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let op1 = self.gpr[REG_SP] as i32;
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let op2 = insn.sword7();
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@ -192,6 +205,7 @@ impl Core {
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ThumbFormat::HiRegOpOrBranchExchange => self.exec_thumb_hi_reg_op_or_bx(bus, insn),
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ThumbFormat::LdrPc => self.exec_thumb_ldr_pc(bus, insn),
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ThumbFormat::LdrStrRegOffset => self.exec_thumb_ldr_str_reg_offset(bus, insn),
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ThumbFormat::LdrStrSp => self.exec_thumb_ldr_str_sp(bus, insn),
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ThumbFormat::AddSp => self.exec_thumb_add_sp(bus, insn),
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ThumbFormat::PushPop => self.exec_thumb_push_pop(bus, insn),
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ThumbFormat::BranchConditional => self.exec_thumb_branch_with_cond(bus, insn),
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