Gotta make clippy happy
Former-commit-id: b2e4b28ae9d054020891029ae0be5e148357779e Former-commit-id: fd0c17e9729f35fd40bd3c75fe53907129776445
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parent
12d9edf5c4
commit
25b630951d
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@ -25,29 +25,20 @@ pub enum AluOpCode {
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impl AluOpCode {
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pub fn is_setting_flags(&self) -> bool {
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use AluOpCode::*;
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match self {
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TST | TEQ | CMP | CMN => true,
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_ => false,
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}
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matches!(self, TST | TEQ | CMP | CMN)
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}
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pub fn is_logical(&self) -> bool {
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use AluOpCode::*;
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match self {
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MOV | MVN | ORR | EOR | AND | BIC | TST | TEQ => true,
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_ => false,
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}
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matches!(self, MOV | MVN | ORR | EOR | AND | BIC | TST | TEQ)
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}
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pub fn is_arithmetic(&self) -> bool {
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use AluOpCode::*;
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match self {
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ADD | ADC | SUB | SBC | RSB | RSC | CMP | CMN => true,
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_ => false,
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}
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matches!(self, ADD | ADC | SUB | SBC | RSB | RSC | CMP | CMN)
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}
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}
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#[derive(Debug, PartialEq, Primitive, Copy, Clone)]
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#[derive(Debug, PartialEq, Eq, Primitive, Copy, Clone)]
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pub enum BarrelShiftOpCode {
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LSL = 0,
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LSR = 1,
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@ -55,13 +46,13 @@ pub enum BarrelShiftOpCode {
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ROR = 3,
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}
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#[derive(Debug, PartialEq, Copy, Clone)]
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#[derive(Debug, PartialEq, Eq, Copy, Clone)]
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pub enum ShiftRegisterBy {
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ByAmount(u32),
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ByRegister(usize),
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}
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#[derive(Debug, PartialEq, Copy, Clone)]
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#[derive(Debug, PartialEq, Eq, Copy, Clone)]
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pub struct ShiftedRegister {
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pub reg: usize,
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pub shift_by: ShiftRegisterBy,
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@ -71,14 +62,11 @@ pub struct ShiftedRegister {
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impl ShiftedRegister {
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pub fn is_shifted_by_reg(&self) -> bool {
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match self.shift_by {
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ShiftRegisterBy::ByRegister(_) => true,
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_ => false,
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}
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matches!(self.shift_by, ShiftRegisterBy::ByRegister(_))
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}
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}
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#[derive(Debug, PartialEq, Copy, Clone)]
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#[derive(Debug, PartialEq, Eq, Copy, Clone)]
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pub enum BarrelShifterValue {
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ImmediateValue(u32),
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RotatedImmediate(u32, u32),
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@ -285,9 +273,7 @@ impl<I: MemoryInterface> Arm7tdmiCore<I> {
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pub fn register_shift(&mut self, shift: &ShiftedRegister, carry: &mut bool) -> u32 {
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match shift.shift_by {
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ShiftRegisterBy::ByAmount(amount) => {
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let result =
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self.barrel_shift_op(shift.bs_op, self.get_reg(shift.reg), amount, carry, true);
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result
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self.barrel_shift_op(shift.bs_op, self.get_reg(shift.reg), amount, carry, true)
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}
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ShiftRegisterBy::ByRegister(rs) => {
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self.shift_by_register(shift.bs_op, shift.reg, rs, carry)
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@ -1,4 +1,4 @@
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use crate::bit::BitIndex;
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use bit::BitIndex;
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use crate::{
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alu::*,
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@ -36,12 +36,12 @@ impl<I: MemoryInterface> Arm7tdmiCore<I> {
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pub fn branch_exchange(&mut self, mut addr: Addr) -> CpuAction {
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if addr.bit(0) {
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addr = addr & !0x1;
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addr &= !0x1;
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self.cpsr.set_state(CpuState::THUMB);
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self.pc = addr;
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self.reload_pipeline16();
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} else {
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addr = addr & !0x3;
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addr &= !0x3;
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self.cpsr.set_state(CpuState::ARM);
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self.pc = addr;
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self.reload_pipeline32();
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@ -101,7 +101,7 @@ impl<I: MemoryInterface> Arm7tdmiCore<I> {
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mask |= 0xff << 8;
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}
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if c {
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mask |= 0xff << 0;
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mask |= 0xff;
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}
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match self.cpsr.mode() {
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@ -186,7 +186,7 @@ impl<I: MemoryInterface> Arm7tdmiCore<I> {
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let shifted_reg = ShiftedRegister {
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reg: reg as usize,
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bs_op: insn.get_bs_op(),
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shift_by: shift_by,
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shift_by,
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added: None,
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};
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self.register_shift(&shifted_reg, &mut carry)
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@ -335,10 +335,8 @@ impl<I: MemoryInterface> Arm7tdmiCore<I> {
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};
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}
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if !LOAD || base_reg != dest_reg {
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if !PRE_INDEX || WRITEBACK{
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self.set_reg(base_reg, effective_addr);
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}
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if (!LOAD || base_reg != dest_reg) && (!PRE_INDEX || WRITEBACK) {
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self.set_reg(base_reg, effective_addr);
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}
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if !PRE_INDEX && WRITEBACK {
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@ -444,12 +442,8 @@ impl<I: MemoryInterface> Arm7tdmiCore<I> {
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};
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}
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if !LOAD || base_reg != dest_reg {
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if !PRE_INDEX {
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self.set_reg(base_reg, effective_addr);
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} else if WRITEBACK {
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self.set_reg(base_reg, effective_addr);
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}
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if (!LOAD || base_reg != dest_reg) && (!PRE_INDEX || WRITEBACK) {
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self.set_reg(base_reg, effective_addr);
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}
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result
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@ -554,16 +548,14 @@ impl<I: MemoryInterface> Arm7tdmiCore<I> {
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} else {
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self.get_reg(r)
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}
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} else if first {
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old_base
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} else {
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if first {
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old_base
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let x = rlist_count * 4;
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if ascending {
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old_base + x
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} else {
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let x = rlist_count * 4;
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if ascending {
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old_base + x
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} else {
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old_base - x
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}
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old_base - x
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}
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};
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@ -14,7 +14,7 @@ use num::FromPrimitive;
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use std::io;
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#[derive(Debug, PartialEq)]
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#[derive(Debug, PartialEq, Eq)]
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pub enum ArmDecodeErrorKind {
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UnknownInstructionFormat,
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DecodedPartDoesNotBelongToInstruction,
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@ -24,7 +24,7 @@ pub enum ArmDecodeErrorKind {
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IoError(io::ErrorKind),
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}
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#[derive(Debug, PartialEq)]
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#[derive(Debug, PartialEq, Eq)]
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pub struct ArmDecodeError {
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pub kind: ArmDecodeErrorKind,
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pub insn: u32,
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@ -34,15 +34,11 @@ pub struct ArmDecodeError {
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#[allow(dead_code)]
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impl ArmDecodeError {
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fn new(kind: ArmDecodeErrorKind, insn: u32, addr: Addr) -> ArmDecodeError {
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ArmDecodeError {
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kind: kind,
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insn: insn,
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addr: addr,
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}
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ArmDecodeError { kind, insn, addr }
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}
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}
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#[derive(Serialize, Deserialize, Debug, Copy, Clone, PartialEq, Primitive)]
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#[derive(Serialize, Deserialize, Debug, Copy, Clone, PartialEq, Eq, Primitive)]
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pub enum ArmCond {
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EQ = 0b0000,
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NE = 0b0001,
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@ -62,7 +58,7 @@ pub enum ArmCond {
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Invalid = 0b1111,
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}
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#[derive(Serialize, Deserialize, Debug, Copy, Clone, PartialEq)]
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#[derive(Serialize, Deserialize, Debug, Copy, Clone, PartialEq, Eq)]
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pub enum ArmFormat {
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BranchExchange = 0,
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BranchLink,
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@ -90,33 +86,33 @@ impl From<u32> for ArmFormat {
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use ArmFormat::*;
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if (0x0fff_fff0 & raw) == 0x012f_ff10 {
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BranchExchange
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} else if (0x0e00_0000 & raw) == 0x0a00_0000 {
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} else if (0x0E00_0000 & raw) == 0x0A00_0000 {
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BranchLink
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} else if (0xe000_0010 & raw) == 0x0600_0000 {
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} else if (0x0E00_0010 & raw) == 0x0600_0000 {
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Undefined
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} else if (0x0fb0_0ff0 & raw) == 0x0100_0090 {
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} else if (0x0FB0_0FF0 & raw) == 0x0100_0090 {
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SingleDataSwap
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} else if (0x0fc0_00f0 & raw) == 0x0000_0090 {
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} else if (0x0FC0_00F0 & raw) == 0x0000_0090 {
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Multiply
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} else if (0x0f80_00f0 & raw) == 0x0080_0090 {
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} else if (0x0F80_00F0 & raw) == 0x0080_0090 {
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MultiplyLong
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} else if (0x0fbf_0fff & raw) == 0x010f_0000 {
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} else if (0x0FBF_0FFF & raw) == 0x010F_0000 {
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MoveFromStatus
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} else if (0x0fbf_fff0 & raw) == 0x0129_f000 {
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} else if (0x0FBF_FFF0 & raw) == 0x0129_F000 {
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MoveToStatus
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} else if (0x0dbf_f000 & raw) == 0x0128_f000 {
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} else if (0x0DBF_F000 & raw) == 0x0128_F000 {
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MoveToFlags
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} else if (0x0c00_0000 & raw) == 0x0400_0000 {
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} else if (0x0C00_0000 & raw) == 0x0400_0000 {
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SingleDataTransfer
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} else if (0x0e40_0F90 & raw) == 0x0000_0090 {
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} else if (0x0E40_0F90 & raw) == 0x0000_0090 {
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HalfwordDataTransferRegOffset
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} else if (0x0e40_0090 & raw) == 0x0040_0090 {
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} else if (0x0E40_0090 & raw) == 0x0040_0090 {
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HalfwordDataTransferImmediateOffset
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} else if (0x0e00_0000 & raw) == 0x0800_0000 {
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} else if (0x0E00_0000 & raw) == 0x0800_0000 {
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BlockDataTransfer
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} else if (0x0f00_0000 & raw) == 0x0f00_0000 {
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} else if (0x0F00_0000 & raw) == 0x0F00_0000 {
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SoftwareInterrupt
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} else if (0x0c00_0000 & raw) == 0x0000_0000 {
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} else if (0x0C00_0000 & raw) == 0x0000_0000 {
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DataProcessing
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} else {
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Undefined
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@ -124,14 +120,14 @@ impl From<u32> for ArmFormat {
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}
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}
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#[derive(Debug, PartialEq, Primitive)]
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#[derive(Debug, PartialEq, Eq, Primitive)]
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pub enum ArmHalfwordTransferType {
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UnsignedHalfwords = 0b01,
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SignedByte = 0b10,
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SignedHalfwords = 0b11,
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}
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#[derive(Serialize, Deserialize, Debug, Clone, PartialEq)]
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#[derive(Serialize, Deserialize, Debug, Clone, PartialEq, Eq)]
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pub struct ArmInstruction {
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pub fmt: ArmFormat,
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pub raw: u32,
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@ -150,11 +146,7 @@ impl InstructionDecoder for ArmInstruction {
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fn decode(raw: u32, addr: Addr) -> Self {
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let fmt = ArmFormat::from(raw);
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ArmInstruction {
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fmt: fmt,
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raw: raw,
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pc: addr,
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}
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ArmInstruction {fmt, raw, pc: addr }
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}
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fn decode_from_bytes(bytes: &[u8], addr: Addr) -> Self {
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@ -166,10 +166,10 @@ impl<I: MemoryInterface> Arm7tdmiCore<I> {
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SavedCpuState {
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cpsr: self.cpsr,
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pc: self.pc,
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gpr: self.gpr.clone(),
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gpr: self.gpr,
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spsr: self.spsr,
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banks: self.banks.clone(),
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pipeline: self.pipeline.clone(),
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pipeline: self.pipeline,
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next_fetch_access: self.next_fetch_access,
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}
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}
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@ -264,8 +264,8 @@ impl<I: MemoryInterface> Arm7tdmiCore<I> {
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}
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}
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pub fn get_registers(&self) -> [u32; 15] {
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self.gpr.clone()
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pub fn copy_registers(&self) -> [u32; 15] {
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self.gpr
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}
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pub(super) fn change_mode(&mut self, old_mode: CpuMode, new_mode: CpuMode) {
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@ -352,7 +352,7 @@ impl<I: MemoryInterface> Arm7tdmiCore<I> {
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#[cfg(feature = "debugger")]
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fn debugger_record_step(&mut self, d: DecodedInstruction) {
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self.dbg.gpr_previous = self.get_registers();
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self.dbg.gpr_previous = self.copy_registers();
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self.dbg.last_executed = Some(d);
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}
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@ -433,12 +433,10 @@ impl<I: MemoryInterface> Arm7tdmiCore<I> {
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self.pipeline[1] = fetched_now;
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let cond = ArmCond::from_u8(insn.bit_range(28..32) as u8)
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.unwrap_or_else(|| unsafe { std::hint::unreachable_unchecked() });
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if cond != ArmCond::AL {
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if !self.check_arm_cond(cond) {
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self.advance_arm();
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self.next_fetch_access = MemoryAccess::NonSeq;
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return;
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}
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if cond != ArmCond::AL && !self.check_arm_cond(cond) {
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self.advance_arm();
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self.next_fetch_access = MemoryAccess::NonSeq;
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return;
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}
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match self.step_arm_exec(insn) {
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CpuAction::AdvancePC(access) => {
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@ -499,7 +497,7 @@ impl<I: MemoryInterface> fmt::Display for Core<I> {
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writeln!(f, "\tGeneral Purpose Registers:")?;
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let reg_normal_style = Style::new().bold();
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let reg_dirty_style = Colour::Black.bold().on(Colour::Yellow);
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let gpr = self.get_registers();
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let gpr = self.copy_registers();
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for i in 0..15 {
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let mut reg_name = reg_string(i).to_string();
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reg_name.make_ascii_uppercase();
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@ -1,4 +1,5 @@
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use std::fmt;
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use std::fmt::Write;
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use std::marker::PhantomData;
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use super::Addr;
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@ -23,7 +24,7 @@ where
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Disassembler {
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base: base as Addr,
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pos: 0,
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bytes: bytes,
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bytes,
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word_size: std::mem::size_of::<D::IntType>(),
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instruction_decoder: PhantomData,
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}
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@ -42,14 +43,9 @@ where
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let addr = self.base + self.pos as Addr;
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let decoded: D = D::decode_from_bytes(&self.bytes[(self.pos as usize)..], addr);
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let decoded_raw = decoded.get_raw();
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self.pos += self.word_size;
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line.push_str(&format!(
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"{:8x}:\t{:08x} \t{}",
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addr,
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decoded.get_raw(),
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decoded
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));
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write!(&mut line, "{addr:8x}:\t{decoded_raw:08x} \t{decoded}").unwrap();
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Some((self.pos as Addr, line))
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}
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}
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|
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@ -2,7 +2,7 @@ use super::memory::MemoryInterface;
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use super::Arm7tdmiCore;
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use super::{CpuMode, CpuState};
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#[derive(Debug, Clone, Copy, PartialEq)]
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#[derive(Debug, Clone, Copy, PartialEq, Eq)]
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#[allow(dead_code)]
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/// Models a CPU exception, and maps to the relavnt entry in the exception vector
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pub enum Exception {
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|
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@ -3,9 +3,6 @@ extern crate serde;
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#[macro_use]
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extern crate enum_primitive_derive;
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use bit;
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use num;
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use num_traits;
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use std::fmt;
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|
@ -35,7 +32,7 @@ pub mod registers_consts {
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pub const REG_SP: usize = 13;
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}
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#[derive(Serialize, Deserialize, Debug, PartialEq, Clone)]
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#[derive(Serialize, Deserialize, Debug, PartialEq, Eq, Clone)]
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pub enum DecodedInstruction {
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Arm(ArmInstruction),
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Thumb(ThumbInstruction),
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|
@ -77,7 +74,7 @@ pub fn reg_string<T: Into<usize>>(reg: T) -> &'static str {
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reg_names[reg.into()]
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}
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#[derive(Debug, PartialEq, Primitive, Copy, Clone)]
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#[derive(Debug, PartialEq, Eq, Primitive, Copy, Clone)]
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#[repr(u8)]
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pub enum CpuState {
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ARM = 0,
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|
@ -94,7 +91,7 @@ impl fmt::Display for CpuState {
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}
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}
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#[derive(Debug, Primitive, Copy, Clone, PartialEq)]
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#[derive(Debug, Primitive, Copy, Clone, PartialEq, Eq)]
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pub enum CpuMode {
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User = 0b10000,
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Fiq = 0b10001,
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|
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@ -28,7 +28,7 @@ impl fmt::Display for MemoryAccess {
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}
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}
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#[derive(Debug, PartialEq, Copy, Clone)]
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#[derive(Debug, PartialEq, Eq, Copy, Clone)]
|
||||
#[repr(u8)]
|
||||
pub enum MemoryAccessWidth {
|
||||
MemoryAccess8 = 0,
|
||||
|
|
|
@ -3,8 +3,8 @@ use std::fmt;
|
|||
|
||||
use serde::{Deserialize, Serialize};
|
||||
|
||||
use crate::bit::BitIndex;
|
||||
use crate::num::FromPrimitive;
|
||||
use bit::BitIndex;
|
||||
use num::FromPrimitive;
|
||||
|
||||
use super::{CpuMode, CpuState};
|
||||
|
||||
|
|
|
@ -428,7 +428,7 @@ impl<I: MemoryInterface> Arm7tdmiCore<I> {
|
|||
}
|
||||
if FLAG_R {
|
||||
pop!(REG_PC);
|
||||
self.pc = self.pc & !1;
|
||||
self.pc &= !1;
|
||||
result = CpuAction::PipelineFlushed;
|
||||
self.reload_pipeline16();
|
||||
}
|
||||
|
@ -482,16 +482,12 @@ impl<I: MemoryInterface> Arm7tdmiCore<I> {
|
|||
if rlist.bit(r) {
|
||||
let v = if r != RB {
|
||||
self.gpr[r]
|
||||
} else {
|
||||
if first {
|
||||
addr
|
||||
} else {
|
||||
addr + (rlist.count_ones() - 1) * 4
|
||||
}
|
||||
};
|
||||
if first {
|
||||
} else if first {
|
||||
first = false;
|
||||
}
|
||||
addr
|
||||
} else {
|
||||
addr + (rlist.count_ones() - 1) * 4
|
||||
};
|
||||
self.store_32(addr, v, access);
|
||||
access = Seq;
|
||||
addr += 4;
|
||||
|
@ -559,7 +555,7 @@ impl<I: MemoryInterface> Arm7tdmiCore<I> {
|
|||
) -> CpuAction {
|
||||
let mut off = insn.offset11();
|
||||
if FLAG_LOW_OFFSET {
|
||||
off = off << 1;
|
||||
off <<= 1;
|
||||
let next_pc = (self.pc - 2) | 1;
|
||||
self.pc = ((self.gpr[REG_LR] & !1) as i32).wrapping_add(off) as u32;
|
||||
self.gpr[REG_LR] = next_pc;
|
||||
|
|
|
@ -10,7 +10,7 @@ use num::FromPrimitive;
|
|||
pub mod disass;
|
||||
pub mod exec;
|
||||
|
||||
#[derive(Serialize, Deserialize, Debug, Copy, Clone, PartialEq)]
|
||||
#[derive(Serialize, Deserialize, Debug, Copy, Clone, PartialEq, Eq)]
|
||||
pub enum ThumbFormat {
|
||||
/// Format 1
|
||||
MoveShiftedReg,
|
||||
|
@ -102,7 +102,7 @@ impl From<u16> for ThumbFormat {
|
|||
}
|
||||
}
|
||||
|
||||
#[derive(Serialize, Deserialize, Debug, Clone, PartialEq)]
|
||||
#[derive(Serialize, Deserialize, Debug, Clone, PartialEq, Eq)]
|
||||
pub struct ThumbInstruction {
|
||||
pub fmt: ThumbFormat,
|
||||
pub raw: u16,
|
||||
|
@ -134,7 +134,7 @@ impl InstructionDecoder for ThumbInstruction {
|
|||
}
|
||||
}
|
||||
|
||||
#[derive(Debug, Primitive, PartialEq)]
|
||||
#[derive(Debug, Primitive, PartialEq, Eq)]
|
||||
pub enum OpFormat3 {
|
||||
MOV = 0,
|
||||
CMP = 1,
|
||||
|
@ -153,7 +153,7 @@ impl From<OpFormat3> for AluOpCode {
|
|||
}
|
||||
}
|
||||
|
||||
#[derive(Debug, Primitive, PartialEq)]
|
||||
#[derive(Debug, Primitive, PartialEq, Eq)]
|
||||
pub enum OpFormat5 {
|
||||
ADD = 0,
|
||||
CMP = 1,
|
||||
|
@ -161,7 +161,7 @@ pub enum OpFormat5 {
|
|||
BX = 3,
|
||||
}
|
||||
|
||||
#[derive(Debug, Primitive, PartialEq)]
|
||||
#[derive(Debug, Primitive, PartialEq, Eq)]
|
||||
pub enum ThumbAluOps {
|
||||
AND = 0b0000,
|
||||
EOR = 0b0001,
|
||||
|
@ -184,17 +184,11 @@ pub enum ThumbAluOps {
|
|||
impl ThumbAluOps {
|
||||
pub fn is_setting_flags(&self) -> bool {
|
||||
use ThumbAluOps::*;
|
||||
match self {
|
||||
TST | CMP | CMN => true,
|
||||
_ => false,
|
||||
}
|
||||
matches!(self, TST | CMP | CMN)
|
||||
}
|
||||
pub fn is_arithmetic(&self) -> bool {
|
||||
use ThumbAluOps::*;
|
||||
match self {
|
||||
ADC | SBC | NEG | CMP | CMN => true,
|
||||
_ => false,
|
||||
}
|
||||
matches!(self, ADC | SBC | NEG | CMP | CMN)
|
||||
}
|
||||
}
|
||||
|
||||
|
|
Reference in a new issue