core: dma: Reduce logs
Former-commit-id: 6db019b583e195fcb6aedb134cf54482a6c72428 Former-commit-id: 9294c305aafac1d55f18f1bd5d2fb5c62db509c5
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@ -88,14 +88,14 @@ impl DmaChannel {
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let timing = ctrl.timing();
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let mut start_immediately = false;
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if ctrl.is_enabled() && !self.ctrl.is_enabled() {
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trace!(
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"DMA{} enabled! timing={} src={:#x} dst={:#x} cnt={}",
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self.id,
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timing,
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self.src,
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self.dst,
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self.wc
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);
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// trace!(
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// "DMA{} enabled! timing={} src={:#x} dst={:#x} cnt={}",
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// self.id,
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// timing,
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// self.src,
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// self.dst,
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// self.wc
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// );
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self.running = true;
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start_immediately = timing == 0;
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self.internal.src_addr = self.src;
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@ -131,6 +131,13 @@ impl Bus for IoDevices {
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REG_DMA1CNT_H => io.dmac.channels[1].ctrl.0,
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REG_DMA2CNT_H => io.dmac.channels[2].ctrl.0,
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REG_DMA3CNT_H => io.dmac.channels[3].ctrl.0,
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// Even though these registers are write only,
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// some games may still try to read them.
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// TODO: should this be treated as an open-bus read?
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REG_DMA0CNT_L => 0,
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REG_DMA1CNT_L => 0,
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REG_DMA2CNT_L => 0,
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REG_DMA3CNT_L => 0,
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REG_WAITCNT => io.waitcnt.0,
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