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core: dma: Reduce logs

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Former-commit-id: 6db019b583e195fcb6aedb134cf54482a6c72428
Former-commit-id: 9294c305aafac1d55f18f1bd5d2fb5c62db509c5
This commit is contained in:
Michel Heily 2020-11-06 05:11:09 -08:00 committed by MishMish
parent 7e2c9d040a
commit 28a57a874a
2 changed files with 15 additions and 8 deletions
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16
core/src/dma.rs
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@ -88,14 +88,14 @@ impl DmaChannel {
let timing = ctrl.timing();
let mut start_immediately = false;
if ctrl.is_enabled() && !self.ctrl.is_enabled() {
trace!(
"DMA{} enabled! timing={} src={:#x} dst={:#x} cnt={}",
self.id,
timing,
self.src,
self.dst,
self.wc
);
// trace!(
// "DMA{} enabled! timing={} src={:#x} dst={:#x} cnt={}",
// self.id,
// timing,
// self.src,
// self.dst,
// self.wc
// );
self.running = true;
start_immediately = timing == 0;
self.internal.src_addr = self.src;

7
core/src/iodev.rs
View file

@ -131,6 +131,13 @@ impl Bus for IoDevices {
REG_DMA1CNT_H => io.dmac.channels[1].ctrl.0,
REG_DMA2CNT_H => io.dmac.channels[2].ctrl.0,
REG_DMA3CNT_H => io.dmac.channels[3].ctrl.0,
// Even though these registers are write only,
// some games may still try to read them.
// TODO: should this be treated as an open-bus read?
REG_DMA0CNT_L => 0,
REG_DMA1CNT_L => 0,
REG_DMA2CNT_L => 0,
REG_DMA3CNT_L => 0,
REG_WAITCNT => io.waitcnt.0,