devraza/rustboyadvance-ng
Archived
1
Fork 0
Code Issues Pull requests Packages Projects Releases 1 Wiki Activity

optimize/arm: Force inlining.

Browse source 
This functions were not inlined by the optimizer


Former-commit-id: aa02a3f5e6d33f16c298bc655c8d3a244c2ef946
This commit is contained in:
Michel Heily 2020-03-28 15:45:16 +03:00 committed by MishMish
parent d9ce1c7d8d
commit 2af9249a6c
2 changed files with 10 additions and 2 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

11
src/core/arm7tdmi/cpu.rs
View file

@ -238,41 +238,48 @@ impl Core {
} }
#[allow(non_snake_case)] #[allow(non_snake_case)]
#[inline(always)]
pub(super) fn S_cycle32(&mut self, sb: &SysBus, addr: u32) { pub(super) fn S_cycle32(&mut self, sb: &SysBus, addr: u32) {
self.cycles += 1; self.cycles += 1;
self.cycles += sb.get_cycles(addr, Seq + MemoryAccess32); self.cycles += sb.get_cycles(addr, Seq + MemoryAccess32);
} }
#[allow(non_snake_case)] #[allow(non_snake_case)]
#[inline(always)]
pub(super) fn S_cycle16(&mut self, sb: &SysBus, addr: u32) { pub(super) fn S_cycle16(&mut self, sb: &SysBus, addr: u32) {
self.cycles += 1; self.cycles += 1;
self.cycles += sb.get_cycles(addr, Seq + MemoryAccess16); self.cycles += sb.get_cycles(addr, Seq + MemoryAccess16);
} }
#[allow(non_snake_case)] #[allow(non_snake_case)]
#[inline(always)]
pub(super) fn S_cycle8(&mut self, sb: &SysBus, addr: u32) { pub(super) fn S_cycle8(&mut self, sb: &SysBus, addr: u32) {
self.cycles += 1; self.cycles += 1;
self.cycles += sb.get_cycles(addr, Seq + MemoryAccess8); self.cycles += sb.get_cycles(addr, Seq + MemoryAccess8);
} }
#[allow(non_snake_case)] #[allow(non_snake_case)]
#[inline(always)]
pub(super) fn N_cycle32(&mut self, sb: &SysBus, addr: u32) { pub(super) fn N_cycle32(&mut self, sb: &SysBus, addr: u32) {
self.cycles += 1; self.cycles += 1;
self.cycles += sb.get_cycles(addr, NonSeq + MemoryAccess32); self.cycles += sb.get_cycles(addr, NonSeq + MemoryAccess32);
} }
#[allow(non_snake_case)] #[allow(non_snake_case)]
#[inline(always)]
pub(super) fn N_cycle16(&mut self, sb: &SysBus, addr: u32) { pub(super) fn N_cycle16(&mut self, sb: &SysBus, addr: u32) {
self.cycles += 1; self.cycles += 1;
self.cycles += sb.get_cycles(addr, NonSeq + MemoryAccess16); self.cycles += sb.get_cycles(addr, NonSeq + MemoryAccess16);
} }
#[allow(non_snake_case)] #[allow(non_snake_case)]
#[inline(always)]
pub(super) fn N_cycle8(&mut self, sb: &SysBus, addr: u32) { pub(super) fn N_cycle8(&mut self, sb: &SysBus, addr: u32) {
self.cycles += 1; self.cycles += 1;
self.cycles += sb.get_cycles(addr, NonSeq + MemoryAccess8); self.cycles += sb.get_cycles(addr, NonSeq + MemoryAccess8);
} }
#[inline]
pub(super) fn check_arm_cond(&self, cond: ArmCond) -> bool { pub(super) fn check_arm_cond(&self, cond: ArmCond) -> bool {
use ArmCond::*; use ArmCond::*;
match cond { match cond {
@ -322,7 +329,7 @@ impl Core {
} }
} }
#[inline] #[inline(always)]
pub fn reload_pipeline16(&mut self, sb: &mut SysBus) { pub fn reload_pipeline16(&mut self, sb: &mut SysBus) {
self.pipeline[0] = sb.read_16(self.pc) as u32; self.pipeline[0] = sb.read_16(self.pc) as u32;
self.N_cycle16(sb, self.pc); self.N_cycle16(sb, self.pc);
@ -332,7 +339,7 @@ impl Core {
self.advance_thumb(); self.advance_thumb();
} }
#[inline] #[inline(always)]
pub fn reload_pipeline32(&mut self, sb: &mut SysBus) { pub fn reload_pipeline32(&mut self, sb: &mut SysBus) {
self.pipeline[0] = sb.read_32(self.pc); self.pipeline[0] = sb.read_32(self.pc);
self.N_cycle16(sb, self.pc); self.N_cycle16(sb, self.pc);

1
src/core/sysbus.rs
View file

@ -208,6 +208,7 @@ impl SysBus {
} }
} }
#[inline(always)]
pub fn get_cycles(&self, addr: Addr, access: MemoryAccess) -> usize { pub fn get_cycles(&self, addr: Addr, access: MemoryAccess) -> usize {
let nonseq_cycles = [4, 3, 2, 8]; let nonseq_cycles = [4, 3, 2, 8];
let seq_cycles = [2, 1]; let seq_cycles = [2, 1];