Minor fixes
Fix LSR integer underflow. Change SWI LR calculation Former-commit-id: 6a298719e380c3a01f70c3b05d9f3507638398d5
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3c3e8c35b4
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3c3129c73c
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@ -129,7 +129,7 @@ impl Core {
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self.bs_carry_out = val.bit(31);
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self.bs_carry_out = val.bit(31);
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0
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0
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}
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}
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x if x < 32 => {
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1..=31 => {
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self.bs_carry_out = val >> (amount - 1) & 1 == 1;
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self.bs_carry_out = val >> (amount - 1) & 1 == 1;
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(val as u32) >> amount
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(val as u32) >> amount
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}
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}
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@ -20,7 +20,7 @@ impl Core {
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ArmFormat::B_BL => self.exec_b_bl(bus, insn),
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ArmFormat::B_BL => self.exec_b_bl(bus, insn),
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ArmFormat::DP => self.exec_data_processing(bus, insn),
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ArmFormat::DP => self.exec_data_processing(bus, insn),
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ArmFormat::SWI => {
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ArmFormat::SWI => {
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self.software_interrupt(bus, insn.pc + 4, insn.swi_comment());
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self.software_interrupt(bus, self.pc - 4, insn.swi_comment());
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Ok(())
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Ok(())
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}
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}
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ArmFormat::LDR_STR => self.exec_ldr_str(bus, insn),
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ArmFormat::LDR_STR => self.exec_ldr_str(bus, insn),
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@ -456,7 +456,6 @@ impl Core {
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self.gpr_banked_r13[5] = 0x0300_7f00; // UND
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self.gpr_banked_r13[5] = 0x0300_7f00; // UND
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self.gpr[13] = 0x0300_7f00;
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self.gpr[13] = 0x0300_7f00;
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self.gpr[14] = 0x0800_0000;
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self.pc = 0x0800_0000;
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self.pc = 0x0800_0000;
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self.cpsr.set(0x5f);
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self.cpsr.set(0x5f);
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@ -563,7 +563,7 @@ impl Core {
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ThumbFormat::LdmStm => self.exec_thumb_ldm_stm(bus, insn),
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ThumbFormat::LdmStm => self.exec_thumb_ldm_stm(bus, insn),
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ThumbFormat::BranchConditional => self.exec_thumb_branch_with_cond(bus, insn),
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ThumbFormat::BranchConditional => self.exec_thumb_branch_with_cond(bus, insn),
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ThumbFormat::Swi => {
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ThumbFormat::Swi => {
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self.software_interrupt(bus, insn.pc + 2, (insn.raw & 0xff) as u32);
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self.software_interrupt(bus, self.pc - 2, (insn.raw & 0xff) as u32);
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Ok(())
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Ok(())
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}
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}
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ThumbFormat::Branch => self.exec_thumb_branch(bus, insn),
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ThumbFormat::Branch => self.exec_thumb_branch(bus, insn),
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