Pass around "Bus" instead of "SysBus"
Former-commit-id: c20dae7dd3ddcb3bd8f671a16fd67a241bd6c459
This commit is contained in:
parent
6f81c236a6
commit
4011911cca
|
@ -13,7 +13,7 @@ use super::{
|
||||||
};
|
};
|
||||||
|
|
||||||
impl Core {
|
impl Core {
|
||||||
pub fn exec_arm(&mut self, sysbus: &mut SysBus, insn: ArmInstruction) -> CpuExecResult {
|
pub fn exec_arm(&mut self, sysbus: &mut Bus, insn: ArmInstruction) -> CpuExecResult {
|
||||||
if !self.check_arm_cond(insn.cond) {
|
if !self.check_arm_cond(insn.cond) {
|
||||||
self.add_cycles(
|
self.add_cycles(
|
||||||
insn.pc + (self.word_size() as u32),
|
insn.pc + (self.word_size() as u32),
|
||||||
|
@ -41,7 +41,7 @@ impl Core {
|
||||||
/// Cycles 2S+1N
|
/// Cycles 2S+1N
|
||||||
fn exec_b_bl(
|
fn exec_b_bl(
|
||||||
&mut self,
|
&mut self,
|
||||||
sysbus: &mut SysBus,
|
sysbus: &mut Bus,
|
||||||
insn: ArmInstruction,
|
insn: ArmInstruction,
|
||||||
) -> CpuResult<CpuPipelineAction> {
|
) -> CpuResult<CpuPipelineAction> {
|
||||||
if insn.link_flag() {
|
if insn.link_flag() {
|
||||||
|
@ -67,7 +67,7 @@ impl Core {
|
||||||
/// Cycles 2S+1N
|
/// Cycles 2S+1N
|
||||||
fn exec_bx(
|
fn exec_bx(
|
||||||
&mut self,
|
&mut self,
|
||||||
sysbus: &mut SysBus,
|
sysbus: &mut Bus,
|
||||||
insn: ArmInstruction,
|
insn: ArmInstruction,
|
||||||
) -> CpuResult<CpuPipelineAction> {
|
) -> CpuResult<CpuPipelineAction> {
|
||||||
let rn = self.get_reg(insn.rn());
|
let rn = self.get_reg(insn.rn());
|
||||||
|
@ -95,7 +95,7 @@ impl Core {
|
||||||
|
|
||||||
fn exec_swi(
|
fn exec_swi(
|
||||||
&mut self,
|
&mut self,
|
||||||
_sysbus: &mut SysBus,
|
_sysbus: &mut Bus,
|
||||||
_insn: ArmInstruction,
|
_insn: ArmInstruction,
|
||||||
) -> CpuResult<CpuPipelineAction> {
|
) -> CpuResult<CpuPipelineAction> {
|
||||||
self.exception(Exception::SoftwareInterrupt);
|
self.exception(Exception::SoftwareInterrupt);
|
||||||
|
@ -104,7 +104,7 @@ impl Core {
|
||||||
|
|
||||||
fn exec_msr_reg(
|
fn exec_msr_reg(
|
||||||
&mut self,
|
&mut self,
|
||||||
sysbus: &mut SysBus,
|
sysbus: &mut Bus,
|
||||||
insn: ArmInstruction,
|
insn: ArmInstruction,
|
||||||
) -> CpuResult<CpuPipelineAction> {
|
) -> CpuResult<CpuPipelineAction> {
|
||||||
let new_psr = RegPSR::new(self.get_reg(insn.rm()));
|
let new_psr = RegPSR::new(self.get_reg(insn.rm()));
|
||||||
|
@ -202,7 +202,7 @@ impl Core {
|
||||||
/// Add x=1I cycles if Op2 shifted-by-register. Add y=1S+1N cycles if Rd=R15.
|
/// Add x=1I cycles if Op2 shifted-by-register. Add y=1S+1N cycles if Rd=R15.
|
||||||
fn exec_data_processing(
|
fn exec_data_processing(
|
||||||
&mut self,
|
&mut self,
|
||||||
sysbus: &mut SysBus,
|
sysbus: &mut Bus,
|
||||||
insn: ArmInstruction,
|
insn: ArmInstruction,
|
||||||
) -> CpuResult<CpuPipelineAction> {
|
) -> CpuResult<CpuPipelineAction> {
|
||||||
// TODO handle carry flag
|
// TODO handle carry flag
|
||||||
|
@ -287,7 +287,7 @@ impl Core {
|
||||||
/// For LDR, add y=1S+1N if Rd=R15.
|
/// For LDR, add y=1S+1N if Rd=R15.
|
||||||
fn exec_ldr_str(
|
fn exec_ldr_str(
|
||||||
&mut self,
|
&mut self,
|
||||||
sysbus: &mut SysBus,
|
sysbus: &mut Bus,
|
||||||
insn: ArmInstruction,
|
insn: ArmInstruction,
|
||||||
) -> CpuResult<CpuPipelineAction> {
|
) -> CpuResult<CpuPipelineAction> {
|
||||||
if insn.write_back_flag() && insn.rd() == insn.rn() {
|
if insn.write_back_flag() && insn.rd() == insn.rn() {
|
||||||
|
|
|
@ -183,7 +183,7 @@ impl Core {
|
||||||
self.cycles += 1;
|
self.cycles += 1;
|
||||||
}
|
}
|
||||||
|
|
||||||
pub fn add_cycles(&mut self, addr: Addr, sysbus: &SysBus, access: MemoryAccess) {
|
pub fn add_cycles(&mut self, addr: Addr, sysbus: &Bus, access: MemoryAccess) {
|
||||||
self.cycles += sysbus.get_cycles(addr, access);
|
self.cycles += sysbus.get_cycles(addr, access);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -210,7 +210,7 @@ impl Core {
|
||||||
|
|
||||||
fn step_thumb(
|
fn step_thumb(
|
||||||
&mut self,
|
&mut self,
|
||||||
sysbus: &mut SysBus,
|
sysbus: &mut Bus,
|
||||||
) -> CpuResult<(Option<DecodedInstruction>, CpuPipelineAction)> {
|
) -> CpuResult<(Option<DecodedInstruction>, CpuPipelineAction)> {
|
||||||
// fetch
|
// fetch
|
||||||
let new_fetched = sysbus.read_16(self.pc);
|
let new_fetched = sysbus.read_16(self.pc);
|
||||||
|
@ -244,7 +244,7 @@ impl Core {
|
||||||
|
|
||||||
fn step_arm(
|
fn step_arm(
|
||||||
&mut self,
|
&mut self,
|
||||||
sysbus: &mut SysBus,
|
sysbus: &mut Bus,
|
||||||
) -> CpuResult<(Option<DecodedInstruction>, CpuPipelineAction)> {
|
) -> CpuResult<(Option<DecodedInstruction>, CpuPipelineAction)> {
|
||||||
// fetch
|
// fetch
|
||||||
let new_fetched = sysbus.read_32(self.pc);
|
let new_fetched = sysbus.read_32(self.pc);
|
||||||
|
@ -278,7 +278,7 @@ impl Core {
|
||||||
|
|
||||||
/// Perform a pipeline step
|
/// Perform a pipeline step
|
||||||
/// If an instruction was executed in this step, return it.
|
/// If an instruction was executed in this step, return it.
|
||||||
pub fn step(&mut self, sysbus: &mut SysBus) -> CpuResult<Option<DecodedInstruction>> {
|
pub fn step(&mut self, sysbus: &mut Bus) -> CpuResult<Option<DecodedInstruction>> {
|
||||||
let (executed_instruction, pipeline_action) = match self.cpsr.state() {
|
let (executed_instruction, pipeline_action) = match self.cpsr.state() {
|
||||||
CpuState::ARM => self.step_arm(sysbus),
|
CpuState::ARM => self.step_arm(sysbus),
|
||||||
CpuState::THUMB => self.step_thumb(sysbus),
|
CpuState::THUMB => self.step_thumb(sysbus),
|
||||||
|
@ -326,7 +326,7 @@ impl Core {
|
||||||
/// A step that returns only once an instruction was executed.
|
/// A step that returns only once an instruction was executed.
|
||||||
/// Returns the address of PC before executing an instruction,
|
/// Returns the address of PC before executing an instruction,
|
||||||
/// and the address of the next instruction to be executed;
|
/// and the address of the next instruction to be executed;
|
||||||
pub fn step_debugger(&mut self, sysbus: &mut SysBus) -> CpuResult<DecodedInstruction> {
|
pub fn step_debugger(&mut self, sysbus: &mut Bus) -> CpuResult<DecodedInstruction> {
|
||||||
loop {
|
loop {
|
||||||
if let Some(i) = self.step(sysbus)? {
|
if let Some(i) = self.step(sysbus)? {
|
||||||
return Ok(i);
|
return Ok(i);
|
||||||
|
|
|
@ -1,9 +1,9 @@
|
||||||
use super::super::super::sysbus::SysBus;
|
|
||||||
use super::super::cpu::{Core, CpuExecResult};
|
use super::super::cpu::{Core, CpuExecResult};
|
||||||
use super::ThumbInstruction;
|
use super::ThumbInstruction;
|
||||||
|
use crate::arm7tdmi::bus::Bus;
|
||||||
|
|
||||||
impl Core {
|
impl Core {
|
||||||
pub fn exec_thumb(&mut self, sysbus: &mut SysBus, insn: ThumbInstruction) -> CpuExecResult {
|
pub fn exec_thumb(&mut self, sysbus: &mut Bus, insn: ThumbInstruction) -> CpuExecResult {
|
||||||
unimplemented!("thumb not implemented {:#}", insn)
|
unimplemented!("thumb not implemented {:#}", insn)
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
|
@ -92,7 +92,7 @@ impl SysBus {
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
fn map(&self, addr: Addr) -> &impl Bus {
|
fn map(&self, addr: Addr) -> & Bus {
|
||||||
match addr as usize {
|
match addr as usize {
|
||||||
0x0000_0000...0x0000_3fff => &self.bios,
|
0x0000_0000...0x0000_3fff => &self.bios,
|
||||||
0x0200_0000...0x0203_ffff => &self.onboard_work_ram,
|
0x0200_0000...0x0203_ffff => &self.onboard_work_ram,
|
||||||
|
@ -107,7 +107,7 @@ impl SysBus {
|
||||||
}
|
}
|
||||||
|
|
||||||
/// TODO proc-macro for generating this function
|
/// TODO proc-macro for generating this function
|
||||||
fn map_mut(&mut self, addr: Addr) -> &mut impl Bus {
|
fn map_mut(&mut self, addr: Addr) -> &mut Bus {
|
||||||
match addr as usize {
|
match addr as usize {
|
||||||
0x0000_0000...0x0000_3fff => &mut self.bios,
|
0x0000_0000...0x0000_3fff => &mut self.bios,
|
||||||
0x0200_0000...0x0203_ffff => &mut self.onboard_work_ram,
|
0x0200_0000...0x0203_ffff => &mut self.onboard_work_ram,
|
||||||
|
|
Reference in a new issue