core: dma: Count cycles passed in DMA transfers
Former-commit-id: 751f2e42f9c5c19f2fcc901754950d1e3797303b Former-commit-id: 30d31be99daec4324532d4663390945a55f641b1
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@ -1,9 +1,9 @@
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use super::arm7tdmi::memory::{MemoryAccess, MemoryInterface};
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use super::cartridge::BackupMedia;
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use super::interrupt::{self, Interrupt, InterruptConnect, SharedInterruptFlags};
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use super::iodev::consts::{REG_FIFO_A, REG_FIFO_B};
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use super::sched::{EventType, Scheduler, SharedScheduler};
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use super::sysbus::SysBus;
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use super::Bus;
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use num::FromPrimitive;
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use serde::{Deserialize, Serialize};
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@ -151,22 +151,26 @@ impl DmaChannel {
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let fifo_mode = self.fifo_mode;
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let mut access = MemoryAccess::NonSeq;
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if fifo_mode {
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for _ in 0..4 {
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let v = sb.read_32(self.internal.src_addr & !3);
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sb.write_32(self.internal.dst_addr & !3, v);
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let v = sb.load_32(self.internal.src_addr & !3, access);
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sb.store_32(self.internal.dst_addr & !3, v, access);
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access = MemoryAccess::Seq;
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self.internal.src_addr += 4;
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}
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} else if word_size == 4 {
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for _ in 0..count {
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let w = sb.read_32(self.internal.src_addr & !3);
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sb.write_32(self.internal.dst_addr & !3, w);
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let w = sb.load_32(self.internal.src_addr & !3, access);
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sb.store_32(self.internal.dst_addr & !3, w, access);
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access = MemoryAccess::Seq;
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self.xfer_adj_addrs(word_size);
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}
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} else {
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for _ in 0..count {
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let hw = sb.read_16(self.internal.src_addr & !1);
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sb.write_16(self.internal.dst_addr & !1, hw);
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let hw = sb.load_16(self.internal.src_addr & !1, access);
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sb.store_16(self.internal.dst_addr & !1, hw, access);
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access = MemoryAccess::Seq;
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self.xfer_adj_addrs(word_size)
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}
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}
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@ -240,7 +244,7 @@ impl DmaController {
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if self.channels[channel_id].write_dma_ctrl(value) {
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// DMA actually starts after 3 cycles
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self.scheduler
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.schedule(EventType::DmaActivateChannel(channel_id), 3);
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.push(EventType::DmaActivateChannel(channel_id), 3);
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} else {
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self.deactivate_channel(channel_id);
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}
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