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arm: Fix STR use of R15 as the base register (Rd)

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Former-commit-id: 696733731a9996ebb90b7d4acf3341facc1ed228
This commit is contained in:
Michel Heily 2019-07-07 22:57:21 +03:00
parent c92bde54a1
commit 45f3bd6264
1 changed files with 5 additions and 1 deletions
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6
src/arm7tdmi/arm/exec.rs
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@ -309,7 +309,11 @@ impl Core {
pipeline_action = CpuPipelineAction::Flush; pipeline_action = CpuPipelineAction::Flush;
} }
} else { } else {
let value = self.get_reg(insn.rd()); let value = if insn.rd() == REG_PC {
insn.pc + 12
} else {
self.get_reg(insn.rd())
};
if insn.transfer_size() == 1 { if insn.transfer_size() == 1 {
self.store_8(addr, value as u8, bus); self.store_8(addr, value as u8, bus);
} else { } else {