optimize: CPU Pipeline optimization part 2
Optimize redundent pipeline stages About 5% performance gain. Also rustfmt.. Former-commit-id: 2f5fc95798e97eb963fea976866bbeaf637084b0
This commit is contained in:
Michel Heily
parent
1f79205f51
commit
6beec306c2
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@ -246,7 +246,13 @@ impl Core {
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}
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}
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pub fn shift_by_register(&mut self, bs_op: BarrelShiftOpCode, reg: usize, rs: usize, carry: bool) -> u32 {
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pub fn shift_by_register(
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&mut self,
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bs_op: BarrelShiftOpCode,
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reg: usize,
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rs: usize,
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carry: bool,
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) -> u32 {
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let mut val = self.get_reg(reg);
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self.add_cycle(); // +1I
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if reg == REG_PC {
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@ -260,7 +266,8 @@ impl Core {
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let carry = self.cpsr.C();
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match shift.shift_by {
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ShiftRegisterBy::ByAmount(amount) => {
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let result = self.barrel_shift_op(shift.bs_op, self.get_reg(shift.reg), amount, carry, true);
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let result =
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self.barrel_shift_op(shift.bs_op, self.get_reg(shift.reg), amount, carry, true);
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result
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}
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ShiftRegisterBy::ByRegister(rs) => {
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@ -3,7 +3,7 @@ use crate::bit::BitIndex;
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use super::super::alu::*;
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use crate::core::arm7tdmi::psr::RegPSR;
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use crate::core::arm7tdmi::CpuAction;
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use crate::core::arm7tdmi::{Core, Addr, CpuMode, CpuState, REG_LR, REG_PC};
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use crate::core::arm7tdmi::{Addr, Core, CpuMode, CpuState, REG_LR, REG_PC};
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use crate::core::sysbus::SysBus;
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use crate::core::Bus;
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@ -92,12 +92,7 @@ impl Core {
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self.write_status_register(sb, insn.spsr_flag(), self.get_reg(insn.rm()))
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}
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fn write_status_register(
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&mut self,
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sb: &mut SysBus,
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is_spsr: bool,
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value: u32,
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) -> CpuAction {
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fn write_status_register(&mut self, sb: &mut SysBus, is_spsr: bool, value: u32) -> CpuAction {
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let new_status_reg = RegPSR::new(value);
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match self.cpsr.mode() {
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CpuMode::User => {
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@ -146,9 +141,7 @@ impl Core {
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BarrelShifterValue::RotatedImmediate(val, amount) => {
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self.ror(val, amount, self.cpsr.C(), false, true)
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}
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BarrelShifterValue::ShiftedRegister(x) => {
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self.register_shift(x)
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}
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BarrelShifterValue::ShiftedRegister(x) => self.register_shift(x),
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_ => unreachable!(),
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}
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}
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@ -616,7 +609,9 @@ impl Core {
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(insn.rd_hi(), insn.rd_lo(), insn.rn(), insn.rs(), insn.rm());
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// check validity
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assert!(!(REG_PC == rd_hi || REG_PC == rd_lo || REG_PC == rn || REG_PC == rs || REG_PC == rm));
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assert!(
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!(REG_PC == rd_hi || REG_PC == rd_lo || REG_PC == rn || REG_PC == rs || REG_PC == rm)
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);
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assert!(!(rd_hi != rd_hi && rd_hi != rm && rd_lo != rm));
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let op1 = self.get_reg(rm);
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@ -1,35 +1,20 @@
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#[cfg(feature = "debugger")]
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use std::fmt;
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#[cfg(feature = "debugger")]
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use ansi_term::{Colour, Style};
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#[cfg(feature = "debugger")]
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use super::reg_string;
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#[cfg(feature = "debugger")]
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use ansi_term::{Colour, Style};
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use serde::{Deserialize, Serialize};
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#[cfg(feature = "debugger")]
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use std::fmt;
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use super::CpuAction;
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pub use super::exception::Exception;
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use super::CpuAction;
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use super::{
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arm::*, psr::RegPSR, thumb::ThumbInstruction, Addr, CpuMode, CpuResult, CpuState,
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DecodedInstruction, InstructionDecoder,
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};
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use crate::core::bus::Bus;
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use crate::core::sysbus::{
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MemoryAccessType::*, MemoryAccessWidth::*, SysBus,
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};
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#[derive(Serialize, Deserialize, Clone, Copy, Debug, PartialEq)]
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pub enum PipelineState {
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Refill1,
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Refill2,
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Execute,
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}
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impl Default for PipelineState {
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fn default() -> PipelineState {
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PipelineState::Refill1
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}
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}
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use crate::core::sysbus::{MemoryAccessType::*, MemoryAccessWidth::*, SysBus};
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#[derive(Serialize, Deserialize, Clone, Debug, Default)]
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pub struct Core {
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@ -48,7 +33,6 @@ pub struct Core {
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pub(super) bs_carry_out: bool,
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pub pipeline_state: PipelineState,
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pipeline: [u32; 2],
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pub last_executed: Option<DecodedInstruction>,
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@ -309,91 +293,77 @@ impl Core {
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}
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}
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pub fn did_pipeline_flush(&self) -> bool {
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self.pipeline_state != PipelineState::Execute
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}
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fn handle_exec_result(&mut self, sb: &mut SysBus, exec_result: CpuAction) {
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match self.cpsr.state() {
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CpuState::ARM => {
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match exec_result {
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CpuAction::AdvancePC => self.advance_arm(),
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CpuAction::FlushPipeline => self.flush_pipeline32(sb),
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}
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}
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CpuState::THUMB => {
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match exec_result {
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CpuAction::AdvancePC => self.advance_thumb(),
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CpuAction::FlushPipeline => self.flush_pipeline16(sb),
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}
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}
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}
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}
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// fn handle_exec_result(&mut self, sb: &mut SysBus, exec_result: CpuAction) {
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// match self.cpsr.state() {
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// CpuState::ARM => {
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// match exec_result {
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// CpuAction::AdvancePC => self.advance_arm(),
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// CpuAction::FlushPipeline => self.reload_pipeline32(sb),
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// }
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// }
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// CpuState::THUMB => {
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// match exec_result {
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// CpuAction::AdvancePC => self.advance_thumb(),
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// CpuAction::FlushPipeline => self.reload_pipeline16(sb),
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// }
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// }
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// }
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// }
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fn step_arm_exec(&mut self, insn: u32, sb: &mut SysBus) {
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let pc = self.pc;
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match self.pipeline_state {
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PipelineState::Refill1 => {
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self.pc = pc.wrapping_add(4);
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self.pipeline_state = PipelineState::Refill2;
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self.last_executed = None;
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}
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PipelineState::Refill2 => {
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self.pc = pc.wrapping_add(4);
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self.pipeline_state = PipelineState::Execute;
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self.last_executed = None;
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}
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PipelineState::Execute => {
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let decoded_arm = ArmInstruction::decode(insn, self.pc.wrapping_sub(8)).unwrap();
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#[cfg(feature = "debugger")]
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{
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self.gpr_previous = self.get_registers();
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}
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self.last_executed = Some(DecodedInstruction::Arm(decoded_arm));
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let result = self.exec_arm(sb, decoded_arm);
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self.handle_exec_result(sb, result);
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}
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let decoded_arm = ArmInstruction::decode(insn, self.pc.wrapping_sub(8)).unwrap();
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#[cfg(feature = "debugger")]
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{
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self.gpr_previous = self.get_registers();
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}
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self.last_executed = Some(DecodedInstruction::Arm(decoded_arm));
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let result = self.exec_arm(sb, decoded_arm);
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match result {
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CpuAction::AdvancePC => self.advance_arm(),
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CpuAction::FlushPipeline => self.reload_pipeline(sb),
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}
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}
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fn step_thumb_exec(&mut self, insn: u16, sb: &mut SysBus) {
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let pc = self.pc;
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match self.pipeline_state {
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PipelineState::Refill1 => {
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self.pc = pc.wrapping_add(2);
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self.pipeline_state = PipelineState::Refill2;
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self.last_executed = None;
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}
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PipelineState::Refill2 => {
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self.pc = pc.wrapping_add(2);
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self.pipeline_state = PipelineState::Execute;
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self.last_executed = None;
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}
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PipelineState::Execute => {
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let decoded_thumb = ThumbInstruction::decode(insn, self.pc.wrapping_sub(4)).unwrap();
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#[cfg(feature = "debugger")]
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{
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self.gpr_previous = self.get_registers();
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}
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self.last_executed = Some(DecodedInstruction::Thumb(decoded_thumb));
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let result = self.exec_thumb(sb, decoded_thumb);
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self.handle_exec_result(sb, result);
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}
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let decoded_thumb = ThumbInstruction::decode(insn, self.pc.wrapping_sub(4)).unwrap();
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#[cfg(feature = "debugger")]
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{
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self.gpr_previous = self.get_registers();
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}
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self.last_executed = Some(DecodedInstruction::Thumb(decoded_thumb));
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let result = self.exec_thumb(sb, decoded_thumb);
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match result {
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CpuAction::AdvancePC => self.advance_thumb(),
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CpuAction::FlushPipeline => self.reload_pipeline(sb),
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}
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}
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#[inline]
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pub(super) fn flush_pipeline16(&mut self, sb: &mut SysBus) {
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self.pipeline_state = PipelineState::Refill1;
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pub(super) fn reload_pipeline16(&mut self, sb: &mut SysBus) {
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self.pipeline[0] = sb.read_16(self.pc) as u32;
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self.N_cycle16(sb, self.pc);
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self.S_cycle16(sb, self.pc + 2);
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self.advance_thumb();
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self.pipeline[1] = sb.read_16(self.pc) as u32;
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self.S_cycle16(sb, self.pc);
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self.advance_thumb();
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}
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#[inline]
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pub(super) fn flush_pipeline32(&mut self, sb: &mut SysBus) {
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self.pipeline_state = PipelineState::Refill1;
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self.N_cycle32(sb, self.pc);
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self.S_cycle32(sb, self.pc + 4);
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pub(super) fn reload_pipeline32(&mut self, sb: &mut SysBus) {
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self.pipeline[0] = sb.read_32(self.pc);
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self.N_cycle16(sb, self.pc);
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self.advance_arm();
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self.pipeline[1] = sb.read_32(self.pc);
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self.S_cycle16(sb, self.pc);
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self.advance_arm();
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}
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#[inline]
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pub(super) fn reload_pipeline(&mut self, sb: &mut SysBus) {
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match self.cpsr.state() {
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CpuState::THUMB => self.reload_pipeline16(sb),
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CpuState::ARM => self.reload_pipeline32(sb),
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}
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}
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#[inline]
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@ -406,23 +376,6 @@ impl Core {
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self.pc = self.pc.wrapping_add(4)
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}
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// fn trace_opcode(&self, insn: u32) {
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// if self.trace_opcodes && self.pipeline_state == PipelineState::Execute {
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// println!("[{:08X}] PC=0x{:08x} | ", insn, self.pc);
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// for r in 0..15 {
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// println!("R{}=0x{:08x} ", r, self.gpr[r]);
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// }
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// println!(
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// " N={} Z={} C={} V={} T={}\n",
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// self.cpsr.N() as u8,
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// self.cpsr.Z() as u8,
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// self.cpsr.C() as u8,
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// self.cpsr.V() as u8,
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// self.cpsr.state() as u8,
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// );
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// }
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// }
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/// Perform a pipeline step
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/// If an instruction was executed in this step, return it.
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pub fn step(&mut self, bus: &mut SysBus) {
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@ -449,11 +402,7 @@ impl Core {
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/// Get's the address of the next instruction that is going to be executed
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pub fn get_next_pc(&self) -> Addr {
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let insn_size = self.word_size() as u32;
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match self.pipeline_state {
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PipelineState::Refill1 => self.pc,
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PipelineState::Refill2 => self.pc - insn_size,
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PipelineState::Execute => self.pc - 2 * insn_size,
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}
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self.pc - 2 * insn_size
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}
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pub fn get_cpu_state(&self) -> CpuState {
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@ -1,5 +1,5 @@
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use super::super::sysbus::SysBus;
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use super::cpu::{Core, PipelineState};
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use super::cpu::Core;
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use super::{CpuMode, CpuState};
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use colored::*;
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@ -59,13 +59,10 @@ impl Core {
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}
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pub fn irq(&mut self, sb: &mut SysBus) {
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if self.pipeline_state != PipelineState::Execute {
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panic!("IRQ when pipeline refilling! {:?}", self.pipeline_state);
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}
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if !self.cpsr.irq_disabled() {
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let lr = self.get_next_pc() + 4;
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self.exception(sb, Exception::Irq, lr);
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self.flush_pipeline32(sb);
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self.reload_pipeline32(sb);
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}
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}
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@ -25,7 +25,7 @@ pub(self) use crate::core::Addr;
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pub enum CpuAction {
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AdvancePC,
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FlushPipeline
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FlushPipeline,
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}
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#[derive(Serialize, Deserialize, Debug, PartialEq, Copy, Clone)]
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@ -22,13 +22,18 @@ impl Core {
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&mut self,
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sb: &mut SysBus,
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insn: ThumbInstruction,
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) -> CpuAction {
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) -> CpuAction {
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let rd = (insn.raw & 0b111) as usize;
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let rs = insn.raw.bit_range(3..6) as usize;
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let shift_amount = insn.offset5() as u8 as u32;
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let op2 = self.barrel_shift_op(insn.format1_op(), self.gpr[rs], shift_amount, self.cpsr.C(), true);
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let op2 = self.barrel_shift_op(
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insn.format1_op(),
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self.gpr[rs],
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shift_amount,
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self.cpsr.C(),
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true,
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);
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self.gpr[rd] = op2;
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self.alu_update_flags(op2, false, self.bs_carry_out, self.cpsr.V());
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@ -148,11 +153,7 @@ impl Core {
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}
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/// Format 5
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fn exec_thumb_hi_reg_op_or_bx(
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&mut self,
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sb: &mut SysBus,
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insn: ThumbInstruction,
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) -> CpuAction {
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fn exec_thumb_hi_reg_op_or_bx(&mut self, sb: &mut SysBus, insn: ThumbInstruction) -> CpuAction {
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let op = insn.format5_op();
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let rd = (insn.raw & 0b111) as usize;
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let dst_reg = if insn.flag(ThumbInstruction::FLAG_H1) {
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@ -172,7 +173,7 @@ impl Core {
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match op {
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OpFormat5::BX => {
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return self.branch_exchange(sb, self.get_reg(src_reg));
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},
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}
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OpFormat5::ADD => {
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self.set_reg(dst_reg, op1.wrapping_add(op2));
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if dst_reg == REG_PC {
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@ -370,11 +371,7 @@ impl Core {
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}
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/// Format 12
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fn exec_thumb_load_address(
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&mut self,
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sb: &mut SysBus,
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insn: ThumbInstruction,
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) -> CpuAction {
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fn exec_thumb_load_address(&mut self, sb: &mut SysBus, insn: ThumbInstruction) -> CpuAction {
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let rd = insn.raw.bit_range(8..11) as usize;
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let result = if insn.flag(ThumbInstruction::FLAG_SP) {
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self.gpr[REG_SP] + (insn.word8() as Addr)
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@ -539,11 +536,7 @@ impl Core {
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}
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/// Format 17
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fn exec_thumb_swi(
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&mut self,
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sb: &mut SysBus,
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_insn: ThumbInstruction,
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) -> CpuAction {
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fn exec_thumb_swi(&mut self, sb: &mut SysBus, _insn: ThumbInstruction) -> CpuAction {
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self.N_cycle16(sb, self.pc);
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self.exception(sb, Exception::SoftwareInterrupt, self.pc - 2);
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@ -1,3 +1,4 @@
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/// Struct containing everything
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use std::cell::RefCell;
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use std::rc::Rc;
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@ -121,10 +122,7 @@ impl GameBoyAdvance {
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}
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fn step_cpu(&mut self, io: &mut IoDevices) -> usize {
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if io.intc.irq_pending()
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&& self.cpu.last_executed.is_some()
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&& !self.cpu.did_pipeline_flush()
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{
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if io.intc.irq_pending() && self.cpu.last_executed.is_some() {
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self.cpu.irq(&mut self.sysbus);
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io.haltcnt = HaltState::Running;
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}
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||||
|
|
@ -215,13 +213,8 @@ mod tests {
|
|||
.build()
|
||||
.unwrap();
|
||||
let dummy = Rc::new(RefCell::new(DummyInterface::new()));
|
||||
let mut gba = GameBoyAdvance::new(
|
||||
bios,
|
||||
cartridge,
|
||||
dummy.clone(),
|
||||
dummy.clone(),
|
||||
dummy.clone(),
|
||||
);
|
||||
let mut gba =
|
||||
GameBoyAdvance::new(bios, cartridge, dummy.clone(), dummy.clone(), dummy.clone());
|
||||
gba.skip_bios();
|
||||
|
||||
gba
|
||||
|
|
|
|||
Reference in a new issue