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Fix SBC and RSC instructions

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Needed to add 1-C and not substract 1-C


Former-commit-id: 339201a2cd41d777d3b3204995e698182032c80d
This commit is contained in:
Michel Heily 2019-08-31 14:10:05 +02:00
parent eab08992b9
commit ba9b4662d4
1 changed files with 5 additions and 3 deletions
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8
src/core/arm7tdmi/alu.rs
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@ -324,8 +324,8 @@ impl Core {
RSB => Self::alu_sub_flags(op2, op1, &mut carry, &mut overflow), RSB => Self::alu_sub_flags(op2, op1, &mut carry, &mut overflow),
ADD | CMN => Self::alu_add_flags(op1, op2, &mut carry, &mut overflow), ADD | CMN => Self::alu_add_flags(op1, op2, &mut carry, &mut overflow),
ADC => Self::alu_add_flags(op1, op2.wrapping_add(C), &mut carry, &mut overflow), ADC => Self::alu_add_flags(op1, op2.wrapping_add(C), &mut carry, &mut overflow),
SBC => Self::alu_sub_flags(op1, op2, &mut carry, &mut overflow).wrapping_sub(1 - C), SBC => Self::alu_sub_flags(op1, op2.wrapping_add(1 - C), &mut carry, &mut overflow),
RSC => Self::alu_sub_flags(op2, op1, &mut carry, &mut overflow).wrapping_sub(1 - C), RSC => Self::alu_sub_flags(op2, op1.wrapping_add(1 - C), &mut carry, &mut overflow),
ORR => op1 | op2, ORR => op1 | op2,
MOV => op2, MOV => op2,
BIC => op1 & (!op2), BIC => op1 & (!op2),
@ -334,9 +334,11 @@ impl Core {
self.cpsr.set_N(result < 0); self.cpsr.set_N(result < 0);
self.cpsr.set_Z(result == 0); self.cpsr.set_Z(result == 0);
self.cpsr.set_C(carry);
if opcode.is_arithmetic() { if opcode.is_arithmetic() {
self.cpsr.set_C(carry);
self.cpsr.set_V(overflow); self.cpsr.set_V(overflow);
} else {
self.cpsr.set_C(self.bs_carry_out)
} }
if opcode.is_setting_flags() { if opcode.is_setting_flags() {