Implement LDR/STR (not tested) and add cycle counting
Former-commit-id: ec9e6bfc2a94291e47d41ff7d839007879d3d694
This commit is contained in:
Michel Heily
parent
98eee121fc
commit
bd053354cb
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@ -1,6 +1,6 @@
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use std::fmt;
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use super::super::{reg_string, REG_PC};
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use crate::arm7tdmi::{Addr, reg_string, REG_PC};
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use super::{
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ArmCond, ArmHalfwordTransferType, ArmInstruction, ArmInstructionFormat, ArmOpCode,
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ArmRegisterShift, ArmShiftType, ArmShiftedValue,
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@ -108,7 +108,7 @@ impl ArmInstruction {
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"b{link}{cond}\t{ofs:#x}",
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link = if self.link_flag() { "l" } else { "" },
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cond = self.cond,
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ofs = 8 + self.pc.wrapping_add(self.branch_offset() as u32) as u32
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ofs = 8 + self.pc.wrapping_add(self.branch_offset() as Addr)
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)
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}
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@ -1,11 +1,11 @@
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use crate::bit::BitIndex;
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use super::super::{
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cpu::{Core, CpuExecResult, CpuPipelineAction},
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exception::Exception,
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sysbus::SysBus,
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CpuError, CpuInstruction, CpuResult, CpuState, REG_PC,
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};
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use crate::arm7tdmi::cpu::{Core, CpuExecResult, CpuPipelineAction};
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use crate::arm7tdmi::exception::Exception;
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use crate::arm7tdmi::bus::{Bus, MemoryAccess, MemoryAccessType::*, MemoryAccessWidth::*};
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use crate::arm7tdmi::{Addr, CpuError, CpuInstruction, CpuResult, CpuState, REG_PC};
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use crate::sysbus::SysBus;
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use super::{
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ArmCond, ArmInstruction, ArmInstructionFormat, ArmOpCode, ArmRegisterShift, ArmShiftType,
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@ -15,6 +15,8 @@ use super::{
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impl Core {
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pub fn exec_arm(&mut self, sysbus: &mut SysBus, insn: ArmInstruction) -> CpuExecResult {
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if !self.check_arm_cond(insn.cond) {
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self.add_cycles(self.pc + (self.word_size() as u32), sysbus, Seq + MemoryAccess32);
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self.add_cycle();
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return Ok(CpuPipelineAction::IncPC);
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}
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match insn.fmt {
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@ -29,23 +31,32 @@ impl Core {
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}
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}
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/// Cycles 2S+1N
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fn exec_b_bl(
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&mut self,
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_sysbus: &mut SysBus,
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sysbus: &mut SysBus,
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insn: ArmInstruction,
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) -> CpuResult<CpuPipelineAction> {
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if self.verbose && insn.cond != ArmCond::Always {
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}
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if insn.link_flag() {
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self.set_reg(14, self.pc & !0b1);
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}
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// +1N
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self.add_cycles(self.pc, sysbus, NonSeq + MemoryAccess32);
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self.pc = (self.pc as i32).wrapping_add(insn.branch_offset()) as u32;
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// +2S
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self.add_cycles(self.pc, sysbus, Seq + MemoryAccess32);
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self.add_cycles(self.pc + (self.word_size() as u32), sysbus, Seq + MemoryAccess32);
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Ok(CpuPipelineAction::Flush)
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}
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/// Cycles 2S+1N
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fn exec_bx(
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&mut self,
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_sysbus: &mut SysBus,
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sysbus: &mut SysBus,
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insn: ArmInstruction,
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) -> CpuResult<CpuPipelineAction> {
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let rn = self.get_reg(insn.rn());
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@ -55,7 +66,15 @@ impl Core {
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self.cpsr.set_state(CpuState::ARM);
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}
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// +1N
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self.add_cycles(self.pc, sysbus, NonSeq + MemoryAccess32);
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self.pc = rn & !1;
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// +2S
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self.add_cycles(self.pc, sysbus, Seq + MemoryAccess32);
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self.add_cycles(self.pc + (self.word_size() as u32), sysbus, Seq + MemoryAccess32);
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Ok(CpuPipelineAction::Flush)
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}
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@ -139,16 +158,28 @@ impl Core {
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}
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}
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/// Logical/Arithmetic ALU operations
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///
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/// Cycles: 1S+x+y (from GBATEK)
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/// Add x=1I cycles if Op2 shifted-by-register. Add y=1S+1N cycles if Rd=R15.
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fn exec_data_processing(
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&mut self,
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_sysbus: &mut SysBus,
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sysbus: &mut SysBus,
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insn: ArmInstruction,
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) -> CpuResult<CpuPipelineAction> {
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// TODO handle carry flag
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let mut pipeline_action = CpuPipelineAction::IncPC;
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let op1 = self.get_reg(insn.rn()) as i32;
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let op2 = insn.operand2()?;
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let rd = insn.rd();
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if rd == REG_PC {
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// +1N
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self.add_cycles(self.pc, sysbus, NonSeq + MemoryAccess32);
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}
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let op2: i32 = match op2 {
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ArmShiftedValue::RotatedImmediate(immediate, rotate) => {
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Ok(immediate.rotate_right(rotate) as i32)
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@ -157,26 +188,123 @@ impl Core {
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reg,
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shift,
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added: _,
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} => self.register_shift(reg, shift),
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} => {
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// +1I
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self.add_cycle();
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self.register_shift(reg, shift)
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}
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_ => unreachable!(),
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}?;
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let opcode = insn.opcode().unwrap();
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let set_flags = opcode.is_setting_flags() || insn.set_cond_flag();
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if let Some(result) = self.alu(opcode, op1, op2, set_flags) {
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self.set_reg(insn.rd(), result as u32)
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self.set_reg(rd, result as u32);
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if (rd == REG_PC) {
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pipeline_action = CpuPipelineAction::Flush;
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// +1S
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self.add_cycles(self.pc, sysbus, Seq + MemoryAccess32);
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}
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}
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Ok(CpuPipelineAction::IncPC)
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// +1S
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self.add_cycles(self.pc + (self.word_size() as u32), sysbus, Seq + MemoryAccess32);
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Ok(pipeline_action)
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}
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fn get_rn_offset(&mut self, insn: &ArmInstruction) -> i32 {
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// TODO decide if error handling or panic here
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match insn.ldr_str_offset().unwrap() {
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ArmShiftedValue::ImmediateValue(offset) => offset,
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ArmShiftedValue::ShiftedRegister {
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reg,
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shift,
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added: Some(added)
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} => {
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let abs = self.register_shift(reg, shift).unwrap();
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if added { abs } else { -abs }
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}
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_ => panic!("bad barrel shift")
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}
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}
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/// Memory Load/Store
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/// Instruction | Cycles | Flags | Expl.
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/// ------------------------------------------------------------------------------
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/// LDR{cond}{B}{T} Rd,<Address> | 1S+1N+1I+y | ---- | Rd=[Rn+/-<offset>]
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/// STR{cond}{B}{T} Rd,<Address> | 2N | ---- | [Rn+/-<offset>]=Rd
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/// ------------------------------------------------------------------------------
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/// For LDR, add y=1S+1N if Rd=R15.
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fn exec_ldr_str(
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&mut self,
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_sysbus: &mut SysBus,
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sysbus: &mut SysBus,
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insn: ArmInstruction,
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) -> CpuResult<CpuPipelineAction> {
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let rn = self.get_reg(insn.rn());
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let rd = self.get_reg(insn.rd());
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if insn.write_back_flag() && insn.rd() == insn.rn() {
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return Err(CpuError::IllegalInstruction);
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}
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let mut pipeline_action = CpuPipelineAction::IncPC;
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let mut addr = self.get_reg(insn.rn());
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if insn.rn() == REG_PC {
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addr += 8; // prefetching
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}
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let dest = self.get_reg(insn.rd());
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let offset = self.get_rn_offset(&insn);
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let effective_addr = (addr as i32).wrapping_add(offset) as Addr;
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addr = if insn.pre_index_flag() {
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effective_addr
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} else {
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addr
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};
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if insn.load_flag() {
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let data = if insn.transfer_size() == 1 {
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// +1N
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self.add_cycles(dest, sysbus, NonSeq + MemoryAccess8);
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sysbus.read_8(addr) as u32
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} else {
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// +1N
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self.add_cycles(dest, sysbus, NonSeq + MemoryAccess32);
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sysbus.read_32(addr)
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};
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// +1S
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self.add_cycles(self.pc + (self.word_size() as u32), sysbus, Seq + MemoryAccess32);
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self.set_reg(insn.rd(), data);
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// +1I
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self.add_cycle();
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// +y
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if insn.rd() == REG_PC {
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// +1S
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self.add_cycles(self.pc, sysbus, Seq + MemoryAccess32);
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// +1N
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self.add_cycles(self.pc + (self.word_size() as u32), sysbus, NonSeq + MemoryAccess32);
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pipeline_action = CpuPipelineAction::Flush;
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}
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} else {
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self.add_cycles(addr, sysbus, NonSeq + MemoryAccess32);
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let value = self.get_reg(insn.rn());
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if insn.transfer_size() == 1 {
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// +1N
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self.add_cycles(dest, sysbus, NonSeq + MemoryAccess8);
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sysbus.write_8(addr, value as u8);
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} else {
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// +1N
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self.add_cycles(dest, sysbus, NonSeq + MemoryAccess32);
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sysbus.write_32(addr, value);
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};
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}
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if insn.write_back_flag() {
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self.set_reg(insn.rn(), effective_addr as u32)
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}
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Ok(CpuPipelineAction::IncPC)
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}
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}
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@ -1,6 +1,8 @@
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pub mod display;
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pub mod exec;
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use crate::arm7tdmi::Addr;
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use crate::bit::BitIndex;
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use crate::num_traits::FromPrimitive;
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use std::convert::TryFrom;
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@ -19,11 +21,11 @@ use ArmDecodeErrorKind::*;
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pub struct ArmDecodeError {
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pub kind: ArmDecodeErrorKind,
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pub insn: u32,
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pub addr: u32,
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pub addr: Addr,
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}
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impl ArmDecodeError {
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fn new(kind: ArmDecodeErrorKind, insn: u32, addr: u32) -> ArmDecodeError {
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fn new(kind: ArmDecodeErrorKind, insn: u32, addr: Addr) -> ArmDecodeError {
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ArmDecodeError {
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kind: kind,
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insn: insn,
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@ -125,13 +127,13 @@ pub struct ArmInstruction {
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pub cond: ArmCond,
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pub fmt: ArmInstructionFormat,
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pub raw: u32,
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pub pc: u32,
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pub pc: Addr,
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}
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impl TryFrom<(u32, u32)> for ArmInstruction {
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impl TryFrom<(u32, Addr)> for ArmInstruction {
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type Error = ArmDecodeError;
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fn try_from(value: (u32, u32)) -> Result<Self, Self::Error> {
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fn try_from(value: (u32, Addr)) -> Result<Self, Self::Error> {
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use ArmInstructionFormat::*;
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let (raw, addr) = value;
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38
src/arm7tdmi/bus.rs
Normal file
38
src/arm7tdmi/bus.rs
Normal file
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@ -0,0 +1,38 @@
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use std::io;
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use std::ops::Add;
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use super::Addr;
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pub enum MemoryAccessType {
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NonSeq,
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Seq
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}
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pub enum MemoryAccessWidth {
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MemoryAccess8,
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MemoryAccess16,
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MemoryAccess32
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}
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impl Add<MemoryAccessWidth> for MemoryAccessType {
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type Output = MemoryAccess;
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fn add(self, other: MemoryAccessWidth) -> Self::Output {
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MemoryAccess(self, other)
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}
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}
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pub struct MemoryAccess(MemoryAccessType, MemoryAccessWidth);
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pub trait Bus {
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fn read_32(&self, addr: Addr) -> u32;
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fn read_16(&self, addr: Addr) -> u16;
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fn read_8(&self, addr: Addr) -> u8;
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fn write_32(&mut self, addr: Addr, value: u32) -> Result<(), io::Error>;
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fn write_16(&mut self, addr: Addr, value: u16) -> Result<(), io::Error>;
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fn write_8(&mut self, addr: Addr, value: u8) -> Result<(), io::Error>;
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fn get_bytes(&self, addr: Addr, size: usize) -> Option<&[u8]>;
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/// returns the number of cycles needed for this memory access
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fn get_cycles(&self, addr: Addr, access: MemoryAccess) -> usize;
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}
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@ -1,16 +1,18 @@
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use std::ops::Add;
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use std::convert::TryFrom;
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use std::fmt;
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use ansi_term::{Colour, Style};
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use super::*;
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use crate::sysbus::SysBus;
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pub use super::exception::Exception;
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use super::psr::RegPSR;
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use super::reg_string;
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use super::sysbus::SysBus;
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type Addr = u32;
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use super::{
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CpuState, CpuMode, reg_string, CpuResult, Addr,
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psr::RegPSR,
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bus::{Bus, MemoryAccess, MemoryAccessType::*, MemoryAccessWidth::*},
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arm::*
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};
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#[derive(Debug, Default)]
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pub struct PipelineContext {
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@ -143,6 +145,18 @@ impl Core {
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self.pc = self.pc.wrapping_add(self.word_size() as u32)
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}
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pub fn cycles(&self) -> usize {
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self.cycles
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}
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pub fn add_cycle(&mut self) {
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self.cycles += 1;
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}
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pub fn add_cycles(&mut self, addr: Addr, sysbus: &SysBus, access: MemoryAccess) {
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self.cycles += sysbus.get_cycles(addr, access);
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}
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pub fn check_arm_cond(&self, cond: ArmCond) -> bool {
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use ArmCond::*;
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match cond {
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@ -176,6 +190,7 @@ impl Core {
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Some((addr, i)) => Some(ArmInstruction::try_from((i, addr)).unwrap()),
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None => None,
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};
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// exec
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let result = match self.pipeline.decoded {
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Some(d) => {
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@ -183,7 +198,9 @@ impl Core {
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let action = self.exec_arm(sysbus, d)?;
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Ok((Some(d), action))
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}
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None => Ok((None, CpuPipelineAction::IncPC)),
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None => {
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Ok((None, CpuPipelineAction::IncPC))
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},
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};
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self.pipeline.fetched = Some((self.pc, new_fetched));
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@ -197,10 +214,6 @@ impl Core {
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/// Perform a pipeline step
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/// If an instruction was executed in this step, return it.
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pub fn step(&mut self, sysbus: &mut SysBus) -> CpuResult<Option<ArmInstruction>> {
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if self.cycles > 0 {
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self.cycles -= 1;
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return Ok(None);
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}
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let (executed_instruction, pipeline_action) = match self.cpsr.state() {
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CpuState::ARM => self.step_arm(sysbus),
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CpuState::THUMB => unimplemented!("thumb not implemented :("),
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@ -220,7 +233,7 @@ impl Core {
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/// Get's the address of the next instruction that is going to be executed
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pub fn get_next_pc(&self) -> Addr {
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if self.pipeline.is_flushed() {
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self.pc
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self.pc as Addr
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} else if self.pipeline.is_only_fetched() {
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self.pipeline.fetched.unwrap().0
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} else if self.pipeline.is_ready_to_execute() {
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@ -245,6 +258,7 @@ impl Core {
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impl fmt::Display for Core {
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fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
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writeln!(f, "ARM7TDMI Core Status:")?;
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writeln!(f, "\tCycles: {}", self.cycles)?;
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writeln!(f, "\tCPSR: {}", self.cpsr)?;
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writeln!(f, "\tGeneral Purpose Registers:")?;
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let reg_normal_style = Style::new().bold();
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@ -1,20 +1,20 @@
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use std::fmt;
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use crate::num_traits::FromPrimitive;
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pub mod arm;
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use arm::*;
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use arm::{ArmInstruction, ArmDecodeError};
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pub mod cpu;
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pub mod bus;
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mod exception;
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mod psr;
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pub use super::sysbus;
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pub const REG_PC: usize = 15;
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pub const REG_LR: usize = 14;
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pub const REG_SP: usize = 13;
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pub type Addr = u32;
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pub fn reg_string(reg: usize) -> &'static str {
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let reg_names = &[
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"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "fp", "ip", "sp", "lr",
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|
|
@ -1,4 +1,5 @@
|
|||
use crate::arm7tdmi::{reg_string, REG_PC};
|
||||
use crate::arm7tdmi::bus::Bus;
|
||||
use crate::debugger::Debugger;
|
||||
use crate::disass::Disassembler;
|
||||
|
||||
|
|
@ -56,7 +57,13 @@ impl Command {
|
|||
break;
|
||||
}
|
||||
match debugger.cpu.step_debugger(&mut debugger.sysbus) {
|
||||
Ok(_) => (),
|
||||
Ok(insn) => {
|
||||
println!(
|
||||
"@0x{:08x}:\n\t{}",
|
||||
insn.pc,
|
||||
Colour::Yellow.italic().paint(format!("{} ", insn))
|
||||
);
|
||||
},
|
||||
Err(e) => {
|
||||
println!("{}: {}", "cpu encountered an error".red(), e);
|
||||
println!("cpu: {:x?}", debugger.cpu);
|
||||
|
|
|
|||
119
src/sysbus.rs
119
src/sysbus.rs
|
|
@ -1,3 +1,8 @@
|
|||
use std::io;
|
||||
|
||||
use super::arm7tdmi::Addr;
|
||||
use super::arm7tdmi::bus::{Bus, MemoryAccess, MemoryAccessType, MemoryAccessWidth};
|
||||
|
||||
use byteorder::{LittleEndian, ReadBytesExt, WriteBytesExt};
|
||||
|
||||
const VIDEO_RAM_SIZE: usize = 128 * 1024;
|
||||
|
|
@ -9,35 +14,119 @@ const BIOS_SIZE: usize = 16 * 1024;
|
|||
const GAMEPAK_ROM_SIZE: usize = 32 * 1024 * 1024;
|
||||
|
||||
#[derive(Debug)]
|
||||
pub struct SysBus {
|
||||
bios_rom: Vec<u8>,
|
||||
}
|
||||
struct BiosROM(Vec<u8>);
|
||||
|
||||
impl SysBus {
|
||||
pub fn new(bios_rom: Vec<u8>) -> SysBus {
|
||||
SysBus { bios_rom: bios_rom }
|
||||
}
|
||||
|
||||
pub fn read_32(&self, addr: u32) -> u32 {
|
||||
impl Bus for BiosROM {
|
||||
fn read_32(&self, addr: Addr) -> u32 {
|
||||
let addr = addr as usize;
|
||||
(&self.bios_rom[addr..addr + 4])
|
||||
(&self.0[addr..addr + 4])
|
||||
.read_u32::<LittleEndian>()
|
||||
.unwrap()
|
||||
}
|
||||
|
||||
pub fn read_16(&self, addr: u32) -> u16 {
|
||||
fn read_16(&self, addr: Addr) -> u16 {
|
||||
let addr = addr as usize;
|
||||
(&self.bios_rom[addr..addr + 4])
|
||||
(&self.0[addr..addr + 4])
|
||||
.read_u16::<LittleEndian>()
|
||||
.unwrap()
|
||||
}
|
||||
|
||||
pub fn get_bytes(&self, addr: u32, size: usize) -> Option<&[u8]> {
|
||||
fn read_8(&self, addr: Addr) -> u8 {
|
||||
self.0[addr as usize]
|
||||
}
|
||||
|
||||
fn write_32(&mut self, addr: Addr, value: u32) -> Result<(), io::Error> {
|
||||
let mut wrt = io::Cursor::new(&mut self.0);
|
||||
wrt.set_position(addr as u64);
|
||||
wrt.write_u32::<LittleEndian>(value)
|
||||
}
|
||||
|
||||
fn write_16(&mut self, addr: Addr, value: u16) -> Result<(), io::Error> {
|
||||
let mut wrt = io::Cursor::new(&mut self.0);
|
||||
wrt.set_position(addr as u64);
|
||||
wrt.write_u16::<LittleEndian>(value)
|
||||
}
|
||||
|
||||
fn write_8(&mut self, addr: Addr, value: u8) -> Result<(), io::Error> {
|
||||
let mut wrt = io::Cursor::new(&mut self.0);
|
||||
wrt.write_u8(value)
|
||||
}
|
||||
|
||||
fn get_bytes(&self, addr: Addr, size: usize) -> Option<&[u8]> {
|
||||
let addr = addr as usize;
|
||||
if addr + size > self.bios_rom.len() {
|
||||
if addr + size > self.0.len() {
|
||||
None
|
||||
} else {
|
||||
Some(&self.bios_rom[addr..addr + size])
|
||||
Some(&self.0[addr..addr + size])
|
||||
}
|
||||
}
|
||||
|
||||
fn get_cycles(&self, _addr: Addr, _access: MemoryAccess) -> usize {
|
||||
1
|
||||
}
|
||||
}
|
||||
|
||||
#[derive(Debug)]
|
||||
enum SysBusDevice {
|
||||
BiosROM(BiosROM)
|
||||
}
|
||||
|
||||
#[derive(Debug)]
|
||||
pub struct SysBus {
|
||||
bios: BiosROM
|
||||
}
|
||||
|
||||
impl SysBus {
|
||||
pub fn new(bios_rom: Vec<u8>) -> SysBus {
|
||||
SysBus { bios: BiosROM(bios_rom) }
|
||||
}
|
||||
|
||||
fn map(&self, addr: Addr) -> & impl Bus {
|
||||
match addr as usize {
|
||||
0...BIOS_SIZE => &self.bios,
|
||||
_ => panic!("unmapped address")
|
||||
}
|
||||
}
|
||||
|
||||
fn map_mut(&mut self, addr: Addr) -> &mut impl Bus {
|
||||
match addr as usize {
|
||||
0...BIOS_SIZE => &mut self.bios,
|
||||
_ => panic!("unmapped address")
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
impl Bus for SysBus {
|
||||
fn read_32(&self, addr: Addr) -> u32 {
|
||||
self.map(addr).read_32(addr)
|
||||
}
|
||||
|
||||
fn read_16(&self, addr: Addr) -> u16 {
|
||||
self.map(addr).read_16(addr)
|
||||
}
|
||||
|
||||
fn read_8(&self, addr: Addr) -> u8 {
|
||||
self.map(addr).read_8(addr)
|
||||
}
|
||||
|
||||
fn write_32(&mut self, addr: Addr, value: u32) -> Result<(), io::Error> {
|
||||
self.map_mut(addr).write_32(addr, value)
|
||||
}
|
||||
|
||||
fn write_16(&mut self, addr: Addr, value: u16) -> Result<(), io::Error> {
|
||||
self.map_mut(addr).write_16(addr, value)
|
||||
}
|
||||
|
||||
fn write_8(&mut self, addr: Addr, value: u8) -> Result<(), io::Error> {
|
||||
self.map_mut(addr).write_8(addr, value)
|
||||
}
|
||||
|
||||
|
||||
fn get_bytes(&self, addr: Addr, size: usize) -> Option<&[u8]> {
|
||||
self.map(addr).get_bytes(addr, size)
|
||||
}
|
||||
|
||||
fn get_cycles(&self, addr: Addr, access: MemoryAccess) -> usize {
|
||||
self.map(addr).get_cycles(addr, access)
|
||||
}
|
||||
}
|
||||
|
|
|
|||
Reference in a new issue