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Fix LSR#0

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Former-commit-id: 7cfcc0b8f6e0849c9090148f2cc381b3419abd39
This commit is contained in:
Michel Heily 2019-12-20 15:06:21 +02:00
parent 11219dab7e
commit cb36db688e
1 changed files with 17 additions and 14 deletions
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21
src/core/arm7tdmi/alu.rs
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@ -122,22 +122,25 @@ impl Core {
} }
} }
pub fn lsr(&mut self, val: u32, amount: u32, _carry_in: bool, immediate: bool) -> u32 { pub fn lsr(&mut self, val: u32, amount: u32, carry_in: bool, immediate: bool) -> u32 {
let amount = if immediate && amount == 0 { 32 } else { amount }; if amount != 0 {
match amount { match amount {
32 => { x if x < 32 => {
self.bs_carry_out = val.bit(31); self.bs_carry_out = (val >> (amount - 1) & 1) == 1;
0 val >> amount
}
1..=31 => {
self.bs_carry_out = val >> (amount - 1) & 1 == 1;
(val as u32) >> amount
} }
_ => { _ => {
self.bs_carry_out = false; self.bs_carry_out = false;
0 0
} }
} }
} else if immediate {
self.bs_carry_out = val.bit(31);
0
} else {
self.bs_carry_out = carry_in;
val
}
} }
pub fn asr(&mut self, val: u32, amount: u32, carry_in: bool, immediate: bool) -> u32 { pub fn asr(&mut self, val: u32, amount: u32, carry_in: bool, immediate: bool) -> u32 {