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armwrestler-fix: Fix MULL_MLAL instructions

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Also fix disassembly for MULL_MLAL


Former-commit-id: f535b2db7edb5d056160699436dbeb0c15e61388
This commit is contained in:
Michel Heily 2019-07-27 18:56:34 +03:00
parent 7429236471
commit e06c77b6fd
2 changed files with 21 additions and 31 deletions
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16
src/core/arm7tdmi/arm/display.rs
View file

@ -352,11 +352,11 @@ impl ArmInstruction {
} }
fn fmt_mull_mlal(&self, f: &mut fmt::Formatter) -> fmt::Result { fn fmt_mull_mlal(&self, f: &mut fmt::Formatter) -> fmt::Result {
if self.accumulate_flag() {
write!( write!(
f, f,
"{sign}mlal{S}{cond}\t{RdLo}, {RdHi}, {Rm}, {Rs}", "{sign}{mnem}{S}{cond}\t{RdLo}, {RdHi}, {Rm}, {Rs}",
sign = self.sign_mark(), sign = self.sign_mark(),
mnem = if self.accumulate_flag() { "mlal" } else { "mull" },
S = self.set_cond_mark(), S = self.set_cond_mark(),
cond = self.cond, cond = self.cond,
RdLo = reg_string(self.rd_lo()), RdLo = reg_string(self.rd_lo()),
@ -364,18 +364,6 @@ impl ArmInstruction {
Rm = reg_string(self.rm()), Rm = reg_string(self.rm()),
Rs = reg_string(self.rs()), Rs = reg_string(self.rs()),
) )
} else {
write!(
f,
"{sign}mull{S}{cond}\t{RdLo}, {RdHi}, {Rm}",
sign = self.sign_mark(),
S = self.set_cond_mark(),
cond = self.cond,
RdLo = reg_string(self.rd_lo()),
RdHi = reg_string(self.rd_hi()),
Rm = reg_string(self.rm())
)
}
} }
fn fmt_ldr_str_hs(&self, f: &mut fmt::Formatter) -> fmt::Result { fn fmt_ldr_str_hs(&self, f: &mut fmt::Formatter) -> fmt::Result {

16
src/core/arm7tdmi/arm/exec.rs
View file

@ -464,13 +464,13 @@ impl Core {
return Err(CpuError::IllegalInstruction); return Err(CpuError::IllegalInstruction);
} }
let op1 = self.get_reg(rm) as u64; let op1 = self.get_reg(rm);
let op2 = self.get_reg(rs) as u64; let op2 = self.get_reg(rs);
let mut result: u64 = if insn.u_flag() { let mut result: u64 = if insn.u_flag() {
// signed // signed
(op1 as i64).wrapping_mul(op2 as i64) as u64 (op1 as i32 as i64).wrapping_mul(op2 as i32 as i64) as u64
} else { } else {
op1.wrapping_mul(op2) (op1 as u64).wrapping_mul(op2 as u64)
}; };
self.add_cycle(); self.add_cycle();
@ -481,8 +481,8 @@ impl Core {
self.add_cycle(); self.add_cycle();
} }
self.set_reg(rd_hi, (result >> 32) as u32); self.set_reg(rd_hi, (result >> 32) as i32 as u32);
self.set_reg(rd_lo, (result & 0xffffffff) as u32); self.set_reg(rd_lo, (result & 0xffffffff) as i32 as u32);
let m = self.get_required_multipiler_array_cycles(self.get_reg(rs) as i32); let m = self.get_required_multipiler_array_cycles(self.get_reg(rs) as i32);
for _ in 0..m { for _ in 0..m {
@ -490,8 +490,10 @@ impl Core {
} }
if insn.set_cond_flag() { if insn.set_cond_flag() {
self.cpsr.set_N((result as i64) < 0); self.cpsr.set_N(result.bit(63));
self.cpsr.set_Z(result == 0); self.cpsr.set_Z(result == 0);
self.cpsr.set_C(false);
self.cpsr.set_V(false);
} }
Ok(()) Ok(())