Start working on Interrupts.
it kinda works now, but needs testing. Former-commit-id: 8510314cce248a737d492d935cf5b48f86d920ed
This commit is contained in:
Michel Heily
parent
66a484e3ae
commit
e962150aaf
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@ -375,7 +375,7 @@ mod tests {
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let mut core = Core::new();
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let bytes = vec![];
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let mut mem = BoxedMemory::new(bytes.into_boxed_slice());
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let mut mem = BoxedMemory::new(bytes.into_boxed_slice(), 0xffff_ffff);
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// swi #0x1337
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let decoded = ArmInstruction::decode(0xef001337, 0).unwrap();
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@ -406,7 +406,7 @@ mod tests {
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core.pc = 0x20 + 8;
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let bytes = vec![];
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let mut mem = BoxedMemory::new(bytes.into_boxed_slice());
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let mut mem = BoxedMemory::new(bytes.into_boxed_slice(), 0xffff_ffff);
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core.exec_arm(&mut mem, decoded).unwrap();
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assert_eq!(core.did_pipeline_flush(), true);
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@ -429,7 +429,7 @@ mod tests {
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core.pc = 0x20 + 8;
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let bytes = vec![];
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let mut mem = BoxedMemory::new(bytes.into_boxed_slice());
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let mut mem = BoxedMemory::new(bytes.into_boxed_slice(), 0xffff_ffff);
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core.exec_arm(&mut mem, decoded).unwrap();
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assert_eq!(core.did_pipeline_flush(), true);
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@ -472,7 +472,7 @@ mod tests {
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/* 20h: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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/* 30h: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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];
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let mut mem = BoxedMemory::new(bytes.into_boxed_slice());
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let mut mem = BoxedMemory::new(bytes.into_boxed_slice(), 0xffff_ffff);
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core.exec_arm(&mut mem, decoded).unwrap();
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assert_eq!(core.gpr[2], 0x1337);
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@ -513,7 +513,7 @@ mod tests {
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/* 20h: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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/* 30h: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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];
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let mut mem = BoxedMemory::new(bytes.into_boxed_slice());
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let mut mem = BoxedMemory::new(bytes.into_boxed_slice(), 0xffff_ffff);
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core.exec_arm(&mut mem, decoded).unwrap();
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assert_eq!(mem.read_32(0), 0xabababab);
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@ -538,7 +538,7 @@ mod tests {
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/* c: */ 0xaa, 0xbb, 0xcc, 0xdd,
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/* 10: */ 0xaa, 0xbb, 0xcc, 0xdd,
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];
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let mut mem = BoxedMemory::new(bytes.into_boxed_slice());
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let mut mem = BoxedMemory::new(bytes.into_boxed_slice(), 0xffff_ffff);
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assert_ne!(mem.read_32(core.get_reg(REG_SP) + 0x10), 0x12345678);
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core.exec_arm(&mut mem, decoded).unwrap();
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@ -36,11 +36,12 @@ impl Core {
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let new_mode = CpuMode::from(e);
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if self.verbose {
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println!(
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"{}: {:?}, pc: {:#x}, new_mode: {:?}",
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"{}: {:?}, pc: {:#x}, new_mode: {:?} old_mode: {:?}",
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"Exception".cyan(),
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e,
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self.pc,
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new_mode
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new_mode,
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self.cpsr.mode(),
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);
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}
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@ -358,7 +358,7 @@ mod tests {
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#[test]
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fn mov_low_reg() {
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let bytes = vec![];
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let mut mem = BoxedMemory::new(bytes.into_boxed_slice());
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let mut mem = BoxedMemory::new(bytes.into_boxed_slice(), 0xffff_ffff);
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let mut core = Core::new();
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core.set_reg(0, 0);
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@ -390,7 +390,7 @@ mod tests {
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/* 8: */ 0x00, 0x00, 0x00, 0x00,
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/* c: */ 0x78, 0x56, 0x34, 0x12,
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];
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let mut mem = BoxedMemory::new(bytes.into_boxed_slice());
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let mut mem = BoxedMemory::new(bytes.into_boxed_slice(), 0xffff_ffff);
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let mut core = Core::new();
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core.set_reg(0, 0);
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@ -420,7 +420,7 @@ mod tests {
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/* 0ch: */ 0xaa, 0xbb, 0xcc, 0xdd,
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/* 10h: */ 0xaa, 0xbb, 0xcc, 0xdd,
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];
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let mut mem = BoxedMemory::new(bytes.into_boxed_slice());
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let mut mem = BoxedMemory::new(bytes.into_boxed_slice(), 0xffff_ffff);
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assert_eq!(format!("{}", str_insn), "str\tr0, [r4, r1]");
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assert_eq!(format!("{}", ldr_insn), "ldrb\tr2, [r4, r1]");
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@ -440,7 +440,7 @@ mod tests {
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/* 08h: */ 0xaa, 0xbb, 0xcc, 0xdd, 0xaa, 0xbb, 0xcc, 0xdd,
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/* 10h: */ 0xaa, 0xbb, 0xcc, 0xdd, 0xaa, 0xbb, 0xcc, 0xdd,
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];
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let mut mem = BoxedMemory::new(bytes.into_boxed_slice());
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let mut mem = BoxedMemory::new(bytes.into_boxed_slice(), 0xffff_ffff);
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core.gpr[4] = 0x12345678;
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core.gpr[3] = 0x2;
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@ -11,6 +11,8 @@ use super::EmuIoDev;
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use super::{GBAError, GBAResult};
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use crate::backend::*;
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use crate::bit::BitIndex;
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pub struct GameBoyAdvance {
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backend: Box<EmulatorBackend>,
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pub cpu: Core,
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@ -86,23 +88,27 @@ impl GameBoyAdvance {
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let previous_cycles = self.cpu.cycles;
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self.cpu.step(&mut self.sysbus).unwrap();
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let cycles = self.cpu.cycles - previous_cycles;
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self.gpu.step(cycles, &mut self.sysbus);
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let (_, irq) = self.gpu.step(cycles, &mut self.sysbus);
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if let Some(irq) = irq {
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self.request_irq(irq);
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}
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}
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fn interrupts_disabled(&self) -> bool {
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self.sysbus.ioregs.read_reg(REG_IME) & 1 == 0
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self.cpu.cpsr.irq_disabled() | (self.sysbus.ioregs.read_reg(REG_IME) & 1 == 0)
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}
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fn request_irq(&mut self, irq: Interrupt) {
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// if self.interrupts_disabled() {
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// return;
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// }
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// let irq_bit = irq as usize;
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// let reg_ie = self.sysbus.ioregs.read_reg(REG_IE);
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// if reg_ie & (1 << irq_bit) != 0 {
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// println!("entering {:?}", irq);
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// self.cpu.exception(Exception::Irq);
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// }
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if self.interrupts_disabled() {
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return;
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}
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let irq_bit_index = irq as usize;
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let reg_ie = self.sysbus.ioregs.read_reg(REG_IE);
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if reg_ie.bit(irq_bit_index) {
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self.sysbus.ioregs.write_reg(REG_IF, (1 << irq_bit_index) as u16);
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println!("entering {:?}", irq);
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self.cpu.exception(Exception::Irq);
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}
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}
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pub fn step(&mut self) -> GBAResult<DecodedInstruction> {
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@ -125,12 +131,10 @@ impl GameBoyAdvance {
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// let (dma_cycles, _) = self.dma3.step(cycles, &mut self.sysbus);
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// cycles += dma_cycles;
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/* let (_, irq) = */
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self.gpu.step(cycles, &mut self.sysbus);
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// if let Some(irq) = irq {
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// self.request_irq(irq);
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// }
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// cycles += lcd_cycles;
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let (_, irq) = self.gpu.step(cycles, &mut self.sysbus);
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if let Some(irq) = irq {
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self.request_irq(irq);
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}
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Ok(executed_insn)
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}
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@ -9,20 +9,32 @@ use super::arm7tdmi::Addr;
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const VIDEO_RAM_SIZE: usize = 128 * 1024;
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const WORK_RAM_SIZE: usize = 256 * 1024;
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const INTERNAL_RAM: usize = 32 * 1024;
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const INTERNAL_RAM_SIZE: usize = 32 * 1024;
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const PALETTE_RAM_SIZE: usize = 1 * 1024;
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const OAM_SIZE: usize = 1 * 1024;
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#[derive(Debug)]
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pub struct BoxedMemory(Box<[u8]>, WaitState);
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impl BoxedMemory {
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pub fn new(boxed_slice: Box<[u8]>) -> BoxedMemory {
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BoxedMemory(boxed_slice, Default::default())
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pub struct BoxedMemory {
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mem: Box<[u8]>,
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ws: WaitState,
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mask: u32,
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}
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pub fn new_with_waitstate(boxed_slice: Box<[u8]>, ws: WaitState) -> BoxedMemory {
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BoxedMemory(boxed_slice, ws)
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impl BoxedMemory {
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pub fn new(boxed_slice: Box<[u8]>, mask: u32) -> BoxedMemory {
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BoxedMemory {
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mem: boxed_slice,
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mask: mask,
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ws: WaitState::default(),
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}
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}
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pub fn new_with_waitstate(boxed_slice: Box<[u8]>, mask: u32, ws: WaitState) -> BoxedMemory {
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BoxedMemory {
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mem: boxed_slice,
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mask: mask,
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ws: ws,
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}
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}
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}
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@ -51,50 +63,52 @@ impl Default for WaitState {
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impl Bus for BoxedMemory {
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fn read_32(&self, addr: Addr) -> u32 {
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(&self.0[addr as usize..])
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(&self.mem[(addr & self.mask) as usize..])
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.read_u32::<LittleEndian>()
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.unwrap()
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}
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fn read_16(&self, addr: Addr) -> u16 {
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(&self.0[addr as usize..])
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(&self.mem[(addr & self.mask) as usize..])
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.read_u16::<LittleEndian>()
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.unwrap()
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}
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fn read_8(&self, addr: Addr) -> u8 {
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(&self.0[addr as usize..])[0]
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(&self.mem[(addr & self.mask) as usize..])[0]
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}
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fn write_32(&mut self, addr: Addr, value: u32) {
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(&mut self.0[addr as usize..])
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(&mut self.mem[(addr & self.mask) as usize..])
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.write_u32::<LittleEndian>(value)
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.unwrap()
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}
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fn write_16(&mut self, addr: Addr, value: u16) {
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(&mut self.0[addr as usize..])
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(&mut self.mem[(addr & self.mask) as usize..])
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.write_u16::<LittleEndian>(value)
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.unwrap()
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}
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fn write_8(&mut self, addr: Addr, value: u8) {
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(&mut self.0[addr as usize..]).write_u8(value).unwrap()
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(&mut self.mem[(addr & self.mask) as usize..])
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.write_u8(value)
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.unwrap()
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}
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fn get_bytes(&self, addr: Addr) -> &[u8] {
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&self.0[addr as usize..]
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&self.mem[(addr & self.mask) as usize..]
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}
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fn get_bytes_mut(&mut self, addr: Addr) -> &mut [u8] {
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&mut self.0[addr as usize..]
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&mut self.mem[(addr & self.mask) as usize..]
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}
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fn get_cycles(&self, _addr: Addr, access: MemoryAccess) -> usize {
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match access.1 {
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MemoryAccessWidth::MemoryAccess8 => self.1.access8,
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MemoryAccessWidth::MemoryAccess16 => self.1.access16,
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MemoryAccessWidth::MemoryAccess32 => self.1.access32,
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MemoryAccessWidth::MemoryAccess8 => self.ws.access8,
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MemoryAccessWidth::MemoryAccess16 => self.ws.access16,
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MemoryAccessWidth::MemoryAccess32 => self.ws.access32,
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}
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}
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}
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@ -151,22 +165,28 @@ pub struct SysBus {
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impl SysBus {
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pub fn new(bios_rom: Vec<u8>, gamepak: Cartridge) -> SysBus {
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SysBus {
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bios: BoxedMemory::new(bios_rom.into_boxed_slice()),
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bios: BoxedMemory::new(bios_rom.into_boxed_slice(), 0xff_ffff),
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onboard_work_ram: BoxedMemory::new_with_waitstate(
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vec![0; WORK_RAM_SIZE].into_boxed_slice(),
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(WORK_RAM_SIZE as u32) - 1,
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WaitState::new(3, 3, 6),
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),
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internal_work_ram: BoxedMemory::new(vec![0; INTERNAL_RAM].into_boxed_slice()),
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internal_work_ram: BoxedMemory::new(
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vec![0; INTERNAL_RAM_SIZE].into_boxed_slice(),
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0x7fff,
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),
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ioregs: IoRegs::default(),
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palette_ram: BoxedMemory::new_with_waitstate(
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vec![0; PALETTE_RAM_SIZE].into_boxed_slice(),
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(PALETTE_RAM_SIZE as u32) - 1,
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WaitState::new(1, 1, 2),
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),
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vram: BoxedMemory::new_with_waitstate(
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vec![0; VIDEO_RAM_SIZE].into_boxed_slice(),
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(VIDEO_RAM_SIZE as u32) - 1,
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WaitState::new(1, 1, 2),
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),
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oam: BoxedMemory::new(vec![0; OAM_SIZE].into_boxed_slice()),
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oam: BoxedMemory::new(vec![0; OAM_SIZE].into_boxed_slice(), (OAM_SIZE as u32) - 1),
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gamepak: gamepak,
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dummy: DummyBus([0; 4]),
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}
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@ -175,11 +195,11 @@ impl SysBus {
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fn map(&self, addr: Addr) -> &Bus {
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match addr as usize {
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0x0000_0000...0x0000_3fff => &self.bios,
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0x0200_0000...0x0203_ffff => &self.onboard_work_ram,
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0x0300_0000...0x0300_7fff => &self.internal_work_ram,
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0x0200_0000...0x02ff_ffff => &self.onboard_work_ram,
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0x0300_0000...0x03ff_ffff => &self.internal_work_ram,
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0x0400_0000...0x0400_03fe => &self.ioregs,
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0x0500_0000...0x0500_03ff => &self.palette_ram,
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0x0600_0000...0x0601_7fff => &self.vram,
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0x0500_0000...0x05ff_ffff => &self.palette_ram,
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0x0600_0000...0x06ff_ffff => &self.vram,
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0x0700_0000...0x0700_03ff => &self.oam,
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0x0800_0000...0x09ff_ffff => &self.gamepak,
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_ => &self.dummy,
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@ -190,11 +210,11 @@ impl SysBus {
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fn map_mut(&mut self, addr: Addr) -> &mut Bus {
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match addr as usize {
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0x0000_0000...0x0000_3fff => &mut self.bios,
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0x0200_0000...0x0203_ffff => &mut self.onboard_work_ram,
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0x0300_0000...0x0300_7fff => &mut self.internal_work_ram,
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0x0200_0000...0x02ff_ffff => &mut self.onboard_work_ram,
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0x0300_0000...0x03ff_ffff => &mut self.internal_work_ram,
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0x0400_0000...0x0400_03fe => &mut self.ioregs,
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0x0500_0000...0x0500_03ff => &mut self.palette_ram,
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0x0600_0000...0x0601_7fff => &mut self.vram,
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0x0500_0000...0x05ff_ffff => &mut self.palette_ram,
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0x0600_0000...0x06ff_ffff => &mut self.vram,
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0x0700_0000...0x0700_03ff => &mut self.oam,
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0x0800_0000...0x09ff_ffff => &mut self.gamepak,
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_ => &mut self.dummy,
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