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Refactor and fix arm condition check

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Former-commit-id: 132c14fc56a21426263971e2d544ff10f072fea1
This commit is contained in:
Michel Heily 2019-07-13 23:32:43 +03:00
parent 1747addcd3
commit fb5229705b
3 changed files with 48 additions and 48 deletions
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30
src/arm7tdmi/arm/display.rs
View file

@ -9,21 +9,21 @@ impl fmt::Display for ArmCond {
fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
use ArmCond::*; use ArmCond::*;
match self { match self {
Equal => write!(f, "eq"), EQ => write!(f, "eq"),
NotEqual => write!(f, "ne"), NE => write!(f, "ne"),
UnsignedHigherOrSame => write!(f, "cs"), HS => write!(f, "cs"),
UnsignedLower => write!(f, "cc"), LO => write!(f, "cc"),
Negative => write!(f, "mi"), MI => write!(f, "mi"),
PositiveOrZero => write!(f, "pl"), PL => write!(f, "pl"),
Overflow => write!(f, "vs"), VS => write!(f, "vs"),
NoOverflow => write!(f, "vc"), VC => write!(f, "vc"),
UnsignedHigher => write!(f, "hi"), HI => write!(f, "hi"),
UnsignedLowerOrSame => write!(f, "ls"), LS => write!(f, "ls"),
GreaterOrEqual => write!(f, "ge"), GE => write!(f, "ge"),
LessThan => write!(f, "lt"), LT => write!(f, "lt"),
GreaterThan => write!(f, "gt"), GT => write!(f, "gt"),
LessThanOrEqual => write!(f, "le"), LE => write!(f, "le"),
Always => write!(f, ""), // the dissasembly should ignore this AL => write!(f, ""), // the dissasembly should ignore this
} }
} }
} }

36
src/arm7tdmi/arm/mod.rs
View file

@ -40,21 +40,21 @@ impl ArmDecodeError {
#[derive(Debug, Copy, Clone, PartialEq, Primitive)] #[derive(Debug, Copy, Clone, PartialEq, Primitive)]
pub enum ArmCond { pub enum ArmCond {
Equal = 0b0000, EQ = 0b0000,
NotEqual = 0b0001, NE = 0b0001,
UnsignedHigherOrSame = 0b0010, HS = 0b0010,
UnsignedLower = 0b0011, LO = 0b0011,
Negative = 0b0100, MI = 0b0100,
PositiveOrZero = 0b0101, PL = 0b0101,
Overflow = 0b0110, VS = 0b0110,
NoOverflow = 0b0111, VC = 0b0111,
UnsignedHigher = 0b1000, HI = 0b1000,
UnsignedLowerOrSame = 0b1001, LS = 0b1001,
GreaterOrEqual = 0b1010, GE = 0b1010,
LessThan = 0b1011, LT = 0b1011,
GreaterThan = 0b1100, GT = 0b1100,
LessThanOrEqual = 0b1101, LE = 0b1101,
Always = 0b1110, AL = 0b1110,
} }
#[derive(Debug, Copy, Clone, PartialEq)] #[derive(Debug, Copy, Clone, PartialEq)]
@ -438,7 +438,7 @@ mod tests {
// ldreq r2, [r5, -r6, lsl #5] // ldreq r2, [r5, -r6, lsl #5]
let decoded = ArmInstruction::decode(0x07_15_22_86, 0).unwrap(); let decoded = ArmInstruction::decode(0x07_15_22_86, 0).unwrap();
assert_eq!(decoded.fmt, ArmFormat::LDR_STR); assert_eq!(decoded.fmt, ArmFormat::LDR_STR);
assert_eq!(decoded.cond, ArmCond::Equal); assert_eq!(decoded.cond, ArmCond::EQ);
assert_eq!(decoded.load_flag(), true); assert_eq!(decoded.load_flag(), true);
assert_eq!(decoded.pre_index_flag(), true); assert_eq!(decoded.pre_index_flag(), true);
assert_eq!(decoded.write_back_flag(), false); assert_eq!(decoded.write_back_flag(), false);
@ -482,7 +482,7 @@ mod tests {
// strteq r2, [r4], -r7, asr #8 // strteq r2, [r4], -r7, asr #8
let decoded = ArmInstruction::decode(0x06_24_24_47, 0).unwrap(); let decoded = ArmInstruction::decode(0x06_24_24_47, 0).unwrap();
assert_eq!(decoded.fmt, ArmFormat::LDR_STR); assert_eq!(decoded.fmt, ArmFormat::LDR_STR);
assert_eq!(decoded.cond, ArmCond::Equal); assert_eq!(decoded.cond, ArmCond::EQ);
assert_eq!(decoded.load_flag(), false); assert_eq!(decoded.load_flag(), false);
assert_eq!(decoded.pre_index_flag(), false); assert_eq!(decoded.pre_index_flag(), false);
assert_eq!(decoded.write_back_flag(), true); assert_eq!(decoded.write_back_flag(), true);
@ -526,7 +526,7 @@ mod tests {
// str r4, [sp, 0x10] // str r4, [sp, 0x10]
let decoded = ArmInstruction::decode(0xe58d4010, 0).unwrap(); let decoded = ArmInstruction::decode(0xe58d4010, 0).unwrap();
assert_eq!(decoded.fmt, ArmFormat::LDR_STR); assert_eq!(decoded.fmt, ArmFormat::LDR_STR);
assert_eq!(decoded.cond, ArmCond::Always); assert_eq!(decoded.cond, ArmCond::AL);
let mut core = Core::new(); let mut core = Core::new();
core.set_reg(4, 0x12345678); core.set_reg(4, 0x12345678);

30
src/arm7tdmi/cpu.rs
View file

@ -256,21 +256,21 @@ impl Core {
pub fn check_arm_cond(&self, cond: ArmCond) -> bool { pub fn check_arm_cond(&self, cond: ArmCond) -> bool {
use ArmCond::*; use ArmCond::*;
match cond { match cond {
Equal => self.cpsr.Z(), EQ => self.cpsr.Z(),
NotEqual => !self.cpsr.Z(), NE => !self.cpsr.Z(),
UnsignedHigherOrSame => self.cpsr.C(), HS => self.cpsr.C(),
UnsignedLower => !self.cpsr.C(), LO => !self.cpsr.C(),
Negative => self.cpsr.N(), MI => self.cpsr.N(),
PositiveOrZero => !self.cpsr.N(), PL => !self.cpsr.N(),
Overflow => self.cpsr.V(), VS => self.cpsr.V(),
NoOverflow => !self.cpsr.V(), VC => !self.cpsr.V(),
UnsignedHigher => self.cpsr.C() && !self.cpsr.Z(), HI => self.cpsr.C() && !self.cpsr.Z(),
UnsignedLowerOrSame => !self.cpsr.C() && self.cpsr.Z(), LS => !self.cpsr.C() || self.cpsr.Z(),
GreaterOrEqual => self.cpsr.N() == self.cpsr.V(), GE => self.cpsr.N() == self.cpsr.V(),
LessThan => self.cpsr.N() != self.cpsr.V(), LT => self.cpsr.N() != self.cpsr.V(),
GreaterThan => !self.cpsr.Z() && (self.cpsr.N() == self.cpsr.V()), GT => !self.cpsr.Z() && (self.cpsr.N() == self.cpsr.V()),
LessThanOrEqual => self.cpsr.Z() || (self.cpsr.N() != self.cpsr.V()), LE => self.cpsr.Z() || (self.cpsr.N() != self.cpsr.V()),
Always => true, AL => true,
} }
} }