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core: Handle lsr 32 correctly

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Shifter tests from the mGBA test suite now pass with a 140/140 score.
Also fixes gba::tests::test_arm7tdmi_thumb_eggvance.

Former-commit-id: 4cd4faa3b33f04969b38480c5eed8bf352be025a
Former-commit-id: d1427d8c9b407be1505c0153cce1ecdadd646664
This commit is contained in:
Tibor Nagy 2020-05-14 14:04:09 +02:00 committed by MishMish
parent 6161892237
commit fe9feb3498
1 changed files with 4 additions and 0 deletions
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rustboyadvance-core/src/arm7tdmi/alu.rs
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@ -138,6 +138,10 @@ impl Core {
self.bs_carry_out = (val >> (amount - 1) & 1) == 1; self.bs_carry_out = (val >> (amount - 1) & 1) == 1;
val >> amount val >> amount
} }
32 => {
self.bs_carry_out = val.bit(31);
0
}
_ => { _ => {
self.bs_carry_out = false; self.bs_carry_out = false;
0 0