Michel Heily
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009e46f6d5
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armwrestler-fix: Properly handle misaligned addresses LDR/LDRH/LDRSH
Former-commit-id: 742a7c2b8413fa9d45df1575a0b14b8d1ab697c4
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2019-07-22 20:25:40 +03:00 |
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Michel Heily
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2fb6f3c884
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Implement (psr / usr bank) transfers for LDM_STM
Former-commit-id: 140e6a6c75f65f08f645b1a0ff2ca7c065438ce4
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2019-07-22 09:21:49 +03:00 |
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Michel Heily
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0b5902c52e
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Implement special MRS
Former-commit-id: 1af358887ef71344987f72d65612095c72565f43
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2019-07-22 09:21:45 +03:00 |
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Michel Heily
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c0d437b1a1
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Fix exceptions and dataprocess mode change
Former-commit-id: 5892131496904b621398212b9dfc077242fa9557
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2019-07-22 01:16:48 +03:00 |
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Michel Heily
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7501adfd12
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Implement thumb17 (Swi)
Former-commit-id: 62d7e14e9b84e74d9236e1f0a5e961ae805f861c
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2019-07-22 01:15:58 +03:00 |
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Michel Heily
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53115a9a58
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Refactor core functionality into a separate module
Former-commit-id: 5d55b9eb0b63ed7c61465b4e814782165caa5002
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2019-07-20 16:46:00 +03:00 |
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