Michel Heily
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3cc84b1b03
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Model many things
Former-commit-id: b87fa2b16b395f497cf217ea043e68404ab2f65e
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2019-07-06 15:54:07 +03:00 |
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Michel Heily
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923032f8cf
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REPL UI changes
Former-commit-id: 6852b86541f967785dbffb6833fc2c11fa5dbef3
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2019-07-04 01:37:47 +03:00 |
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Michel Heily
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6f81c236a6
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Mega Commit #2 - Add some thumb decoding and disassembly
Former-commit-id: e3a89ac681a8d6f6f0bee85b32f64d181e11242f
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2019-07-03 00:03:35 +03:00 |
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Michel Heily
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05fb40c17c
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debugger: Add Deref expression.
i.e:
r5 = *r6
r5 = *(u8*)r6
r5 = *(u16*)0x08000000
Former-commit-id: 962dade8e3c0b9f291115285137cf51b0abde266
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2019-07-02 13:36:52 +03:00 |
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Michel Heily
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6b225d776d
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Implement all memory mappings. Reformat many files.
Former-commit-id: c0a62b610e62d2db2a4daf4aeef40068820daa52
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2019-07-01 17:45:29 +03:00 |
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Michel Heily
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bd053354cb
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Implement LDR/STR (not tested) and add cycle counting
Former-commit-id: ec9e6bfc2a94291e47d41ff7d839007879d3d694
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2019-06-30 16:59:37 +03:00 |
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Michel Heily
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967ccca8dd
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Mega commit - model CPU pipelining.
I except many bugs to arise..
Former-commit-id: bcc6ea57af803f783b0dd548b50956b3ccda2b1a
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2019-06-29 22:23:12 +03:00 |
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Michel Heily
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c90448075f
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debugger: Fix breakpoint hit message
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2019-06-28 15:07:29 +03:00 |
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Michel Heily
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b9d1d38c2d
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debugger: Few improvements
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2019-06-27 13:16:00 +03:00 |
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