Michel Heily
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53115a9a58
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Refactor core functionality into a separate module
Former-commit-id: 5d55b9eb0b63ed7c61465b4e814782165caa5002
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2019-07-20 16:46:00 +03:00 |
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Michel Heily
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a9bf2d25e0
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arm: Implement Arm MSR_FLAGS
Former-commit-id: 64d2cf255304ecca02dadc55266d22bc1f92bb4c
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2019-07-10 22:35:40 +03:00 |
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Michel Heily
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3cc84b1b03
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Model many things
Former-commit-id: b87fa2b16b395f497cf217ea043e68404ab2f65e
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2019-07-06 15:54:07 +03:00 |
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Michel Heily
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cbddeffd91
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arm: Implement MSR_REG and fix some prefetching errors
Former-commit-id: 177b8966159ed86472b0d4d031363df72d46807a
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2019-07-02 16:53:29 +03:00 |
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Michel Heily
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967ccca8dd
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Mega commit - model CPU pipelining.
I except many bugs to arise..
Former-commit-id: bcc6ea57af803f783b0dd548b50956b3ccda2b1a
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2019-06-29 22:23:12 +03:00 |
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Michel Heily
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1a0725f1a3
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cpu: Model exceptions
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2019-06-27 15:13:38 +03:00 |
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Michel Heily
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1d766e95de
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cpu: Fix bug in psr mode bits
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2019-06-27 15:03:44 +03:00 |
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Michel Heily
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5808c03fcd
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cpu: Model Program Status Register.
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2019-06-27 13:15:46 +03:00 |
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