According to GBATEK:
The SAD, DAD, and CNT_L registers are holding the initial start
addresses, and initial length. The hardware does NOT change the content
of these registers during or after the transfer.
The actual transfer takes place by using internal pointer/counter
registers. The initial values are copied into internal regs under the
following circumstances:
Upon DMA Enable (Bit 15) changing from 0 to 1: Reloads SAD, DAD, CNT_L.
Upon Repeat: Reloads CNT_L, and optionally DAD (Increment+Reload).
Former-commit-id: 1e606dc88603a4600a79a341ef17fe8ccb482871
I have fought very hard against the rust ownership model,
In the end for DMA to play nice with my code, I had to resort to use
unsafe code for now..
The DMA implementation itself is not accurate to say the least, but will
have to do for now.
Tonc's dma_demo.gba plays but with a visual glitch.
Former-commit-id: 3b9cdcb2d09c78701290f2c48b77f9f3487e85c9
This commit refactors the ioregs:
* Use bitfield crate to implement the GPU ioregs.
* IoRegs are stored in their own variables bindings (i.e, Gpu related ioregs are now fields of the Gpu struct)
- This optimize performance quiet alot from my testings - since every scanline was accessing deseralizing ioregs from sysbus. (Getting constant 59fps now)
* For now, comment out DMA model
Also, cleaned the code up to eliminate rustc warnings.
Former-commit-id: 9077695c446ebd1a71783acfdd9819245aa02d7a
