260 lines
7.1 KiB
Rust
260 lines
7.1 KiB
Rust
use std::collections::VecDeque;
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use super::arm7tdmi::{Addr, Bus};
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use super::sysbus::SysBus;
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use super::{Interrupt, IrqBitmask};
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use num::FromPrimitive;
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#[derive(Debug)]
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enum DmaTransferType {
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Xfer16bit,
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Xfer32bit,
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}
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#[derive(Debug)]
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pub struct DmaChannel {
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id: usize,
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pub src: u32,
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pub dst: u32,
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pub wc: u32,
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pub ctrl: DmaChannelCtrl,
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// These are "latched" when the dma is enabled.
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internal: DmaInternalRegs,
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running: bool,
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cycles: usize,
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start_cycles: usize,
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fifo_mode: bool,
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irq: Interrupt,
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}
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#[derive(Debug, Default)]
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struct DmaInternalRegs {
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src_addr: u32,
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dst_addr: u32,
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count: u32,
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}
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impl DmaChannel {
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pub fn new(id: usize) -> DmaChannel {
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if id > 3 {
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panic!("invalid dma id {}", id);
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}
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DmaChannel {
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id: id,
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irq: Interrupt::from_usize(id + 8).unwrap(),
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running: false,
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src: 0,
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dst: 0,
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wc: 0,
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ctrl: DmaChannelCtrl(0),
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cycles: 0,
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start_cycles: 0,
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fifo_mode: false,
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internal: Default::default(),
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}
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}
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pub fn is_running(&self) -> bool {
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self.running
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}
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pub fn write_src_low(&mut self, low: u16) {
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let src = self.src;
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self.src = (src & 0xffff0000) | (low as u32);
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}
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pub fn write_src_high(&mut self, high: u16) {
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let src = self.src;
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let high = high as u32;
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self.src = (src & 0xffff) | (high << 16);
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}
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pub fn write_dst_low(&mut self, low: u16) {
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let dst = self.dst;
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self.dst = (dst & 0xffff0000) | (low as u32);
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}
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pub fn write_dst_high(&mut self, high: u16) {
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let dst = self.dst;
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let high = high as u32;
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self.dst = (dst & 0xffff) | (high << 16);
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}
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pub fn write_word_count(&mut self, value: u16) {
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self.wc = value as u32;
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}
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pub fn write_dma_ctrl(&mut self, value: u16) -> bool {
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let ctrl = DmaChannelCtrl(value);
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let timing = ctrl.timing();
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let mut start_immediately = false;
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if ctrl.is_enabled() && !self.ctrl.is_enabled() {
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self.start_cycles = self.cycles;
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self.running = true;
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start_immediately = timing == 0;
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self.internal.src_addr = self.src;
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self.internal.dst_addr = self.dst;
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self.internal.count = self.wc;
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self.fifo_mode = timing == 3 && (self.id == 0 || self.id == 1);
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}
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self.ctrl = ctrl;
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return start_immediately;
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}
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#[inline]
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fn xfer_adj_addrs(&mut self, word_size: u32) {
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match self.ctrl.src_adj() {
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/* Increment */ 0 => self.internal.src_addr += word_size,
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/* Decrement */ 1 => self.internal.src_addr -= word_size,
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/* Fixed */ 2 => {}
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_ => panic!("forbidden DMA source address adjustment"),
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}
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match self.ctrl.dst_adj() {
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/* Increment[+Reload] */ 0 | 3 => self.internal.dst_addr += word_size,
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/* Decrement */ 1 => self.internal.dst_addr -= word_size,
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/* Fixed */ 2 => {}
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_ => panic!("forbidden DMA dest address adjustment"),
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}
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}
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fn xfer(&mut self, sb: &mut SysBus, irqs: &mut IrqBitmask) {
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let word_size = if self.ctrl.is_32bit() { 4 } else { 2 };
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let count = match self.internal.count {
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0 => match self.id {
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3 => 0x1_0000,
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_ => 0x0_4000,
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},
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_ => self.internal.count,
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};
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let fifo_mode = self.fifo_mode;
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if fifo_mode {
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println!("FIFO Tranfer");
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for _ in 0..count {
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let v = sb.read_16(self.internal.src_addr);
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sb.write_16(self.internal.dst_addr, v);
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self.internal.src_addr += 2;
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}
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} else if word_size == 4 {
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for _ in 0..count {
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let w = sb.read_32(self.internal.src_addr);
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sb.write_32(self.internal.dst_addr, w);
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self.xfer_adj_addrs(word_size);
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}
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} else {
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for _ in 0..count {
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let hw = sb.read_16(self.internal.src_addr);
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sb.write_16(self.internal.dst_addr, hw);
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self.xfer_adj_addrs(word_size)
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}
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}
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if self.ctrl.is_triggering_irq() {
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irqs.add_irq(self.irq);
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}
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if self.ctrl.repeat() {
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self.start_cycles = self.cycles;
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/* reload */
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if 3 == self.ctrl.dst_adj() {
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self.internal.dst_addr = self.dst;
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}
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} else {
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self.running = false;
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self.ctrl.set_enabled(false);
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}
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}
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}
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#[derive(Debug)]
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pub struct DmaController {
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pub channels: [DmaChannel; 4],
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xfers_queue: VecDeque<usize>,
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cycles: usize,
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}
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impl DmaController {
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pub fn new() -> DmaController {
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DmaController {
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channels: [
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DmaChannel::new(0),
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DmaChannel::new(1),
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DmaChannel::new(2),
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DmaChannel::new(3),
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],
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xfers_queue: VecDeque::new(),
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cycles: 0,
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}
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}
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pub fn perform_work(&mut self, sb: &mut SysBus, irqs: &mut IrqBitmask) -> bool {
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if self.xfers_queue.is_empty() {
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false
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} else {
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while let Some(id) = self.xfers_queue.pop_front() {
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self.channels[id].xfer(sb, irqs)
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}
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true
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}
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}
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pub fn write_16(&mut self, channel_id: usize, ofs: u32, value: u16) {
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match ofs {
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0 => self.channels[channel_id].write_src_low(value),
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2 => self.channels[channel_id].write_src_high(value),
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4 => self.channels[channel_id].write_dst_low(value),
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6 => self.channels[channel_id].write_dst_high(value),
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8 => self.channels[channel_id].write_word_count(value),
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10 => {
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if self.channels[channel_id].write_dma_ctrl(value) {
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self.xfers_queue.push_back(channel_id)
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}
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}
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_ => panic!("Invalid dma offset"),
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}
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}
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pub fn notify_vblank(&mut self) {
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for i in 0..4 {
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if self.channels[i].ctrl.is_enabled() && self.channels[i].ctrl.timing() == 1 {
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self.xfers_queue.push_back(i);
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}
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}
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}
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pub fn notify_hblank(&mut self) {
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for i in 0..4 {
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if self.channels[i].ctrl.is_enabled() && self.channels[i].ctrl.timing() == 2 {
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self.xfers_queue.push_back(i);
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}
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}
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}
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pub fn notify_sound_fifo(&mut self, fifo_addr: u32) {
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for i in 1..=2 {
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if self.channels[i].ctrl.is_enabled()
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&& self.channels[i].ctrl.timing() == 3
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&& self.channels[i].dst == fifo_addr
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{
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self.xfers_queue.push_back(i);
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}
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}
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}
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}
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bitfield! {
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#[derive(Default)]
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pub struct DmaChannelCtrl(u16);
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impl Debug;
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u16;
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dst_adj, _ : 6, 5;
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src_adj, _ : 8, 7;
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repeat, _ : 9;
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is_32bit, _: 10;
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timing, _: 13, 12;
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is_triggering_irq, _: 14;
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is_enabled, set_enabled: 15;
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}
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