Commit graph

18 commits

Author SHA1 Message Date
Michel Heily aee86d85c8 Start Sdl2AudioPlayer
Former-commit-id: 905b846d751db577bc213f1ca38a4c0e72558cfa
2019-12-20 15:11:26 +02:00
Michel Heily 04d2edfc01 Refactor "backend" concept
See plat/sdl2


Former-commit-id: 5f7c9625467003d5b73307959095eb5365db523e
2019-12-20 15:11:26 +02:00
Michel Heily 1d088accb8 mGBA test suite now boots!
Fix tons of bug and reimplemented some of the core code.
Add a neat feature for debug builds:
When the cpu "swi 0x55" instruction, a breakpoint is triggered on the
host.


Former-commit-id: 959249df4374327d90b2503d7a45f8d5d27995a6
2019-11-12 18:22:00 +02:00
Michel Heily 7cc1a50d12 Support zip files and add --no-framerate-limit
Former-commit-id: 62a7122fb0b3e832eeb3cbf347a0966e4cd32d50
2019-09-11 21:26:40 +03:00
Michel Heily 639993edd7 Add blending and mosaic SFX, and cleanup code.
Former-commit-id: b9f0ccaf1820da61f49ebeb2af5beff5cccd722f
2019-08-13 22:15:36 +03:00
Michel Heily 3f6a52cae6 Add sdl2 backend
Currently has bad performance


Former-commit-id: 384ef6b5cd7b1e1baeb6adfbc0b299b0d07d7a5d
2019-08-10 18:14:59 +03:00
Michel Heily c7dd713605 The big ioregs refactoring.
This commit refactors the ioregs:
* Use bitfield crate to implement the GPU ioregs.
* IoRegs are stored in their own variables bindings (i.e, Gpu related ioregs are now fields of the Gpu struct)
  - This optimize performance quiet alot from my testings - since every scanline was accessing deseralizing ioregs from sysbus. (Getting constant 59fps now)
* For now, comment out DMA model

Also, cleaned the code up to eliminate rustc warnings.


Former-commit-id: 9077695c446ebd1a71783acfdd9819245aa02d7a
2019-08-03 00:24:15 +03:00
Michel Heily eb2a1a02fe Implement background scrolling!
tonc's brin_demo.gba now works as intended :)


Former-commit-id: 596c063c5968534f42e42f52203c85262b9c6fa2
2019-07-31 00:52:46 +03:00
Michel Heily 7e9c0e31da Add minifb backend - Armwrestler now plays !
Former-commit-id: d72ea9139e04624322cf3bc4a8ab330f6bb133a4
2019-07-20 23:02:18 +03:00
Michel Heily 53115a9a58 Refactor core functionality into a separate module
Former-commit-id: 5d55b9eb0b63ed7c61465b4e814782165caa5002
2019-07-20 16:46:00 +03:00
Michel Heily 7119ba2451 Cpu: Rewrite pipeline code.
Pipeline code was unreadable up until now, this also fixes a bug:

* Some roms have illegal instructions right after branch instructions, and
the cpu would error trying to decode them because of pipelining.


Former-commit-id: e3201c7b0d2adfc772231a3e2d5909f43c17b50f
2019-07-20 16:03:37 +03:00
Michel Heily 1f074e20ad Refactor lcd -> gpu
Former-commit-id: c12be139770922bac55490c76348f5406fc00f07
2019-07-16 01:21:11 +03:00
Michel Heily c92bde54a1 Begin modeling DMA
Former-commit-id: 83ab601e70666f76ed3ebfb22340c6b1868af3ac
2019-07-07 01:47:51 +03:00
Michel Heily 3cc84b1b03 Model many things
Former-commit-id: b87fa2b16b395f497cf217ea043e68404ab2f65e
2019-07-06 15:54:07 +03:00
Michel Heily 58e1230e7a Model the cartidge.
Former-commit-id: b51d2928631bfc438b9f1b15fafcaa9d90008179
2019-07-03 01:40:08 +03:00
Michel Heily 6f81c236a6 Mega Commit #2 - Add some thumb decoding and disassembly
Former-commit-id: e3a89ac681a8d6f6f0bee85b32f64d181e11242f
2019-07-03 00:03:35 +03:00
Michel Heily cbddeffd91 arm: Implement MSR_REG and fix some prefetching errors
Former-commit-id: 177b8966159ed86472b0d4d031363df72d46807a
2019-07-02 16:53:29 +03:00
Michel Heily 22c175d9cc Reorganize package structure
Former-commit-id: d7ad26c07fc7063522fae061577f7ceece797ae5
2019-07-01 16:15:42 +03:00