6 commits

Author	SHA1	Message	Date
Michel Heily	967ccca8dd	Mega commit - model CPU pipelining. ... I except many bugs to arise.. Former-commit-id: bcc6ea57af803f783b0dd548b50956b3ccda2b1a	2019-06-29 22:23:12 +03:00
Michel Heily	d11620e65b	cpu: Add SWI instruction ... Also cleanup code, and add a test for swi decoding	2019-06-28 11:46:36 +03:00
Michel Heily	1a0725f1a3	cpu: Model exceptions	2019-06-27 15:13:38 +03:00
Michel Heily	6552329310	cpu: Kinda implement data processing instructions ... When I say "Kinda", I mean that it is not tested well.	2019-06-27 13:16:00 +03:00
Michel Heily	9330c53957	Start modeling CPU ... Wrote a shallow skeleton of a CPU Core. Finally made the disassembler a clap subcommand.	2019-06-27 13:15:19 +03:00
Michel Heily	addea1efa0	Merge both packages	2019-06-24 22:02:00 +03:00

Renamed from arm7tdmi/src/lib.rs (Browse further)