Michel Heily
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05fb40c17c
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debugger: Add Deref expression.
i.e:
r5 = *r6
r5 = *(u8*)r6
r5 = *(u16*)0x08000000
Former-commit-id: 962dade8e3c0b9f291115285137cf51b0abde266
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2019-07-02 13:36:52 +03:00 |
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Michel Heily
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6b225d776d
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Implement all memory mappings. Reformat many files.
Former-commit-id: c0a62b610e62d2db2a4daf4aeef40068820daa52
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2019-07-01 17:45:29 +03:00 |
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Michel Heily
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967ccca8dd
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Mega commit - model CPU pipelining.
I except many bugs to arise..
Former-commit-id: bcc6ea57af803f783b0dd548b50956b3ccda2b1a
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2019-06-29 22:23:12 +03:00 |
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Michel Heily
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fc6410b510
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debugger: Make prompt bold
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2019-06-27 15:04:15 +03:00 |
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Michel Heily
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b9d1d38c2d
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debugger: Few improvements
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2019-06-27 13:16:00 +03:00 |
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Michel Heily
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8a057ba159
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debugger: Remember last command
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2019-06-27 13:15:46 +03:00 |
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Michel Heily
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587ec3fc91
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debugger: Add history to repl
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2019-06-27 13:15:46 +03:00 |
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Michel Heily
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f45a856835
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Support assignment expressions for registers!
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2019-06-27 13:15:46 +03:00 |
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Michel Heily
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f1f33d8586
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Improve debugger repl parsing.
Add assignment expressions, add tests, and cleanup code.
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2019-06-27 13:15:46 +03:00 |
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Michel Heily
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fc400ace5f
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Improve debug repl parsing :)
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2019-06-27 13:15:46 +03:00 |
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