0665ff7451
Former-commit-id: 8a103161f34eb1a6c731c63ae65ca1056117ec55 Former-commit-id: 74c8158e7354253f6bd4ad50488d34de34e3ad70
724 lines
24 KiB
Rust
724 lines
24 KiB
Rust
use crate::bit::BitIndex;
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use super::super::alu::*;
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use crate::arm7tdmi::psr::RegPSR;
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use crate::arm7tdmi::CpuAction;
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use crate::arm7tdmi::{Addr, Core, CpuMode, CpuState, REG_LR, REG_PC};
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use super::super::memory::{MemoryAccess, MemoryInterface};
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use MemoryAccess::*;
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use super::ArmDecodeHelper;
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use super::*;
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impl<I: MemoryInterface> Core<I> {
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#[cfg(not(feature = "arm7tdmi_dispatch_table"))]
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pub fn exec_arm(&mut self, insn: u32, fmt: ArmFormat) -> CpuAction {
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match fmt {
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ArmFormat::BranchExchange => self.exec_arm_bx(insn),
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ArmFormat::BranchLink => self.exec_arm_b_bl(insn),
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ArmFormat::DataProcessing => self.exec_arm_data_processing(insn),
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ArmFormat::SoftwareInterrupt => self.exec_arm_swi(insn),
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ArmFormat::SingleDataTransfer => self.exec_arm_ldr_str(insn),
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ArmFormat::HalfwordDataTransferImmediateOffset => self.exec_arm_ldr_str_hs_imm(insn),
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ArmFormat::HalfwordDataTransferRegOffset => self.exec_arm_ldr_str_hs_reg(insn),
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ArmFormat::BlockDataTransfer => self.exec_arm_ldm_stm(insn),
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ArmFormat::MoveFromStatus => self.exec_arm_mrs(insn),
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ArmFormat::MoveToStatus => self.exec_arm_transfer_to_status(insn),
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ArmFormat::MoveToFlags => self.exec_arm_transfer_to_status(insn),
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ArmFormat::Multiply => self.exec_arm_mul_mla(insn),
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ArmFormat::MultiplyLong => self.exec_arm_mull_mlal(insn),
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ArmFormat::SingleDataSwap => self.exec_arm_swp(insn),
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ArmFormat::Undefined => self.arm_undefined(insn),
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}
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}
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pub fn arm_undefined(&mut self, insn: u32) -> CpuAction {
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panic!(
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"executing undefined arm instruction {:08x} at @{:08x}",
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insn,
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self.pc_arm()
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)
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}
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/// Branch and Branch with Link (B, BL)
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/// Execution Time: 2S + 1N
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pub fn exec_arm_b_bl<const LINK: bool>(&mut self, insn: u32) -> CpuAction {
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if LINK {
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self.set_reg(REG_LR, (self.pc_arm() + (self.word_size() as u32)) & !0b1);
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}
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self.pc = (self.pc as i32).wrapping_add(insn.branch_offset()) as u32 & !1;
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self.reload_pipeline32(); // Implies 2S + 1N
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CpuAction::PipelineFlushed
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}
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pub fn branch_exchange(&mut self, mut addr: Addr) -> CpuAction {
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if addr.bit(0) {
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addr = addr & !0x1;
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self.cpsr.set_state(CpuState::THUMB);
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self.pc = addr;
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self.reload_pipeline16();
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} else {
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addr = addr & !0x3;
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self.cpsr.set_state(CpuState::ARM);
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self.pc = addr;
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self.reload_pipeline32();
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}
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CpuAction::PipelineFlushed
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}
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/// Branch and Exchange (BX)
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/// Cycles 2S+1N
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pub fn exec_arm_bx(&mut self, insn: u32) -> CpuAction {
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self.branch_exchange(self.get_reg(insn.bit_range(0..4) as usize))
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}
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/// Move from status register
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/// 1S
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pub fn exec_arm_mrs(&mut self, insn: u32) -> CpuAction {
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let rd = insn.bit_range(12..16) as usize;
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let result = if insn.spsr_flag() {
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self.spsr.get()
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} else {
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self.cpsr.get()
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};
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self.set_reg(rd, result);
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CpuAction::AdvancePC(Seq)
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}
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#[inline(always)]
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fn decode_msr_param(&mut self, insn: u32) -> u32 {
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if insn.bit(25) {
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let immediate = insn & 0xff;
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let rotate = 2 * insn.bit_range(8..12);
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let mut carry = self.cpsr.C();
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let v = self.ror(immediate, rotate, &mut carry, false, true);
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self.cpsr.set_C(carry);
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v
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} else {
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self.get_reg((insn & 0b1111) as usize)
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}
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}
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/// Move to status register
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/// 1S
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pub fn exec_arm_transfer_to_status(&mut self, insn: u32) -> CpuAction {
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let value = self.decode_msr_param(insn);
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let f = insn.bit(19);
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let s = insn.bit(18);
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let x = insn.bit(17);
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let c = insn.bit(16);
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let mut mask = 0;
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if f {
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mask |= 0xff << 24;
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}
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if s {
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mask |= 0xff << 16;
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}
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if x {
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mask |= 0xff << 8;
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}
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if c {
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mask |= 0xff << 0;
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}
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let is_spsr = insn.spsr_flag();
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match self.cpsr.mode() {
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CpuMode::User => {
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if is_spsr {
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panic!("User mode can't access SPSR")
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}
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self.cpsr.set_flag_bits(value);
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}
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_ => {
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if is_spsr {
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self.spsr.set(value);
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} else {
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let old_mode = self.cpsr.mode();
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let new_psr = RegPSR::new((self.cpsr.get() & !mask) | (value & mask));
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let new_mode = new_psr.mode();
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if old_mode != new_mode {
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self.change_mode(old_mode, new_mode);
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}
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self.cpsr = new_psr;
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}
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}
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}
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CpuAction::AdvancePC(Seq)
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}
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fn transfer_spsr_mode(&mut self) {
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let spsr = self.spsr;
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if self.cpsr.mode() != spsr.mode() {
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self.change_mode(self.cpsr.mode(), spsr.mode());
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}
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self.cpsr = spsr;
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}
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/// Logical/Arithmetic ALU operations
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///
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/// Cycles: 1S+x+y (from GBATEK)
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/// Add x=1I cycles if Op2 shifted-by-register. Add y=1S+1N cycles if Rd=R15.
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pub fn exec_arm_data_processing<
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const OP: u8,
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const IMM: bool,
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const SET_FLAGS: bool,
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const SHIFT_BY_REG: bool,
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>(
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&mut self,
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insn: u32,
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) -> CpuAction {
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use AluOpCode::*;
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let rn = insn.bit_range(16..20) as usize;
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let rd = insn.bit_range(12..16) as usize;
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let mut op1 = if rn == REG_PC {
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self.pc_arm() + 8
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} else {
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self.get_reg(rn)
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};
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let mut s_flag = SET_FLAGS;
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let opcode =
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AluOpCode::from_u8(OP).unwrap_or_else(|| unsafe { std::hint::unreachable_unchecked() });
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let mut carry = self.cpsr.C();
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let op2 = if IMM {
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let immediate = insn & 0xff;
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let rotate = 2 * insn.bit_range(8..12);
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// TODO refactor out
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self.ror(immediate, rotate, &mut carry, false, true)
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} else {
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let reg = insn & 0xf;
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let shift_by = if SHIFT_BY_REG {
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if rn == REG_PC {
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op1 += 4;
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}
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self.idle_cycle();
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let rs = insn.bit_range(8..12) as usize;
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ShiftRegisterBy::ByRegister(rs)
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} else {
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let amount = insn.bit_range(7..12) as u32;
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ShiftRegisterBy::ByAmount(amount)
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};
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let shifted_reg = ShiftedRegister {
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reg: reg as usize,
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bs_op: insn.get_bs_op(),
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shift_by: shift_by,
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added: None,
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};
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self.register_shift(&shifted_reg, &mut carry)
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};
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if rd == REG_PC && s_flag {
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self.transfer_spsr_mode();
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s_flag = false;
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}
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let alu_res = if s_flag {
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let mut overflow = self.cpsr.V();
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let result = match opcode {
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AND | TST => op1 & op2,
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EOR | TEQ => op1 ^ op2,
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SUB | CMP => self.alu_sub_flags(op1, op2, &mut carry, &mut overflow),
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RSB => self.alu_sub_flags(op2, op1, &mut carry, &mut overflow),
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ADD | CMN => self.alu_add_flags(op1, op2, &mut carry, &mut overflow),
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ADC => self.alu_adc_flags(op1, op2, &mut carry, &mut overflow),
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SBC => self.alu_sbc_flags(op1, op2, &mut carry, &mut overflow),
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RSC => self.alu_sbc_flags(op2, op1, &mut carry, &mut overflow),
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ORR => op1 | op2,
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MOV => op2,
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BIC => op1 & (!op2),
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MVN => !op2,
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};
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self.alu_update_flags(result, opcode.is_arithmetic(), carry, overflow);
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if opcode.is_setting_flags() {
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None
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} else {
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Some(result)
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}
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} else {
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let c = carry as u32;
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Some(match opcode {
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AND => op1 & op2,
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EOR => op1 ^ op2,
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SUB => op1.wrapping_sub(op2),
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RSB => op2.wrapping_sub(op1),
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ADD => op1.wrapping_add(op2),
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ADC => op1.wrapping_add(op2).wrapping_add(c),
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SBC => op1.wrapping_sub(op2.wrapping_add(1 - c)),
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RSC => op2.wrapping_sub(op1.wrapping_add(1 - c)),
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ORR => op1 | op2,
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MOV => op2,
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BIC => op1 & (!op2),
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MVN => !op2,
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_ => panic!("DataProcessing should be a PSR transfer"),
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})
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};
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let mut result = CpuAction::AdvancePC(Seq);
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if let Some(alu_res) = alu_res {
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self.set_reg(rd, alu_res as u32);
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if rd == REG_PC {
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// T bit might have changed
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match self.cpsr.state() {
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CpuState::ARM => self.reload_pipeline32(),
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CpuState::THUMB => self.reload_pipeline16(),
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};
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result = CpuAction::PipelineFlushed;
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}
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}
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result
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}
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/// Memory Load/Store
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/// Instruction | Cycles | Flags | Expl.
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/// ------------------------------------------------------------------------------
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/// LDR{cond}{B}{T} Rd,<Address> | 1S+1N+1I+y | ---- | Rd=[Rn+/-<offset>]
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/// STR{cond}{B}{T} Rd,<Address> | 2N | ---- | [Rn+/-<offset>]=Rd
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/// ------------------------------------------------------------------------------
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/// For LDR, add y=1S+1N if Rd=R15.
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pub fn exec_arm_ldr_str<
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const LOAD: bool,
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const WRITEBACK: bool,
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const PRE_INDEX: bool,
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const BYTE: bool,
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const SHIFT: bool,
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const ADD: bool,
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const BS_OP: u8,
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const SHIFT_BY_REG: bool,
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>(
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&mut self,
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insn: u32,
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) -> CpuAction {
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let mut result = CpuAction::AdvancePC(NonSeq);
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let base_reg = insn.bit_range(16..20) as usize;
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let dest_reg = insn.bit_range(12..16) as usize;
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let mut addr = self.get_reg(base_reg);
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if base_reg == REG_PC {
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addr = self.pc_arm() + 8; // prefetching
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}
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let mut offset = insn.bit_range(0..12);
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if SHIFT {
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let mut carry = self.cpsr.C();
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let rm = offset & 0xf;
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offset =
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self.register_shift_const::<BS_OP, SHIFT_BY_REG>(offset, rm as usize, &mut carry);
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}
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let offset = if ADD {
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offset as u32
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} else {
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(-(offset as i32)) as u32
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};
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let effective_addr = (addr as i32).wrapping_add(offset as i32) as Addr;
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// TODO - confirm this
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let old_mode = self.cpsr.mode();
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if !PRE_INDEX && WRITEBACK {
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self.change_mode(old_mode, CpuMode::User);
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}
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addr = if PRE_INDEX { effective_addr } else { addr };
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if LOAD {
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let data = if BYTE {
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self.load_8(addr, NonSeq) as u32
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} else {
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self.ldr_word(addr, NonSeq)
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};
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self.set_reg(dest_reg, data);
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// +1I
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self.idle_cycle();
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if dest_reg == REG_PC {
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self.reload_pipeline32();
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result = CpuAction::PipelineFlushed;
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}
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} else {
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let value = if dest_reg == REG_PC {
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self.pc_arm() + 12
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} else {
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self.get_reg(dest_reg)
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};
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if insn.transfer_size() == 1 {
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self.store_8(addr, value as u8, NonSeq);
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} else {
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self.store_aligned_32(addr & !0x3, value, NonSeq);
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};
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}
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if !LOAD || base_reg != dest_reg {
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if !PRE_INDEX {
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self.set_reg(base_reg, effective_addr);
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} else if WRITEBACK {
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self.set_reg(base_reg, effective_addr);
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}
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}
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if !PRE_INDEX && WRITEBACK {
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self.change_mode(self.cpsr.mode(), old_mode);
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}
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result
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}
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pub fn exec_arm_ldr_str_hs_reg(&mut self, insn: u32) -> CpuAction {
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let offset = {
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let added = insn.add_offset_flag();
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let abs = self.get_reg((insn & 0xf) as usize);
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if added {
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abs as u32
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} else {
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(-(abs as i32)) as u32
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}
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};
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self.ldr_str_hs_common(insn, offset)
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}
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pub fn exec_arm_ldr_str_hs_imm(&mut self, insn: u32) -> CpuAction {
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let offset8 = (insn.bit_range(8..12) << 4) + insn.bit_range(0..4);
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let offset8 = if insn.add_offset_flag() {
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offset8
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} else {
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(-(offset8 as i32)) as u32
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};
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self.ldr_str_hs_common(insn, offset8)
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}
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#[inline(always)]
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pub fn ldr_str_hs_common(&mut self, insn: u32, offset: u32) -> CpuAction {
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let mut result = CpuAction::AdvancePC(NonSeq);
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let load = insn.load_flag();
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let pre_index = insn.pre_index_flag();
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let writeback = insn.write_back_flag();
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let base_reg = insn.bit_range(16..20) as usize;
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let dest_reg = insn.bit_range(12..16) as usize;
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let mut addr = self.get_reg(base_reg);
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if base_reg == REG_PC {
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addr = self.pc_arm() + 8; // prefetching
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}
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// TODO - confirm this
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let old_mode = self.cpsr.mode();
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if !pre_index && writeback {
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self.change_mode(old_mode, CpuMode::User);
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}
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let effective_addr = (addr as i32).wrapping_add(offset as i32) as Addr;
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addr = if insn.pre_index_flag() {
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effective_addr
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} else {
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addr
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};
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if load {
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let data = match insn.halfword_data_transfer_type() {
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ArmHalfwordTransferType::SignedByte => self.load_8(addr, NonSeq) as u8 as i8 as u32,
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ArmHalfwordTransferType::SignedHalfwords => self.ldr_sign_half(addr, NonSeq),
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ArmHalfwordTransferType::UnsignedHalfwords => self.ldr_half(addr, NonSeq),
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};
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self.set_reg(dest_reg, data);
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// +1I
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self.idle_cycle();
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if dest_reg == REG_PC {
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self.reload_pipeline32();
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result = CpuAction::PipelineFlushed;
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}
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} else {
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let value = if dest_reg == REG_PC {
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self.pc_arm() + 12
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} else {
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self.get_reg(dest_reg)
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};
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match insn.halfword_data_transfer_type() {
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ArmHalfwordTransferType::UnsignedHalfwords => {
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self.store_aligned_16(addr, value as u16, NonSeq);
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}
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_ => panic!("invalid HS flags for L=0"),
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};
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}
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if !load || base_reg != dest_reg {
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if !pre_index {
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self.set_reg(base_reg, effective_addr);
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} else if insn.write_back_flag() {
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self.set_reg(base_reg, effective_addr);
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}
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}
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result
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}
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pub fn exec_arm_ldm_stm(&mut self, insn: u32) -> CpuAction {
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let mut result = CpuAction::AdvancePC(NonSeq);
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let mut full = insn.pre_index_flag();
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let ascending = insn.add_offset_flag();
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let s_flag = insn.bit(22);
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let is_load = insn.load_flag();
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let mut writeback = insn.write_back_flag();
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let base_reg = insn.bit_range(16..20) as usize;
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let mut base_addr = self.get_reg(base_reg);
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let rlist = insn.register_list();
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if s_flag {
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match self.cpsr.mode() {
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CpuMode::User | CpuMode::System => {
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panic!("LDM/STM with S bit in unprivileged mode")
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}
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_ => {}
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};
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}
|
|
|
|
let user_bank_transfer = if s_flag {
|
|
if is_load {
|
|
!rlist.bit(REG_PC)
|
|
} else {
|
|
true
|
|
}
|
|
} else {
|
|
false
|
|
};
|
|
|
|
let old_mode = self.cpsr.mode();
|
|
if user_bank_transfer {
|
|
self.change_mode(old_mode, CpuMode::User);
|
|
}
|
|
|
|
let psr_transfer = s_flag & is_load & rlist.bit(REG_PC);
|
|
|
|
let rlist_count = rlist.count_ones();
|
|
|
|
let old_base = base_addr;
|
|
|
|
if rlist != 0 && !ascending {
|
|
base_addr = base_addr.wrapping_sub(rlist_count * 4);
|
|
if writeback {
|
|
self.set_reg(base_reg, base_addr);
|
|
writeback = false;
|
|
}
|
|
full = !full;
|
|
}
|
|
|
|
let mut addr = base_addr;
|
|
|
|
if rlist != 0 {
|
|
if is_load {
|
|
let mut access = NonSeq;
|
|
for r in 0..16 {
|
|
if rlist.bit(r) {
|
|
if r == base_reg {
|
|
writeback = false;
|
|
}
|
|
if full {
|
|
addr = addr.wrapping_add(4);
|
|
}
|
|
let val = self.load_32(addr, access);
|
|
access = Seq;
|
|
self.set_reg(r, val);
|
|
if r == REG_PC {
|
|
if psr_transfer {
|
|
self.transfer_spsr_mode();
|
|
}
|
|
self.reload_pipeline32();
|
|
result = CpuAction::PipelineFlushed;
|
|
}
|
|
if !full {
|
|
addr = addr.wrapping_add(4);
|
|
}
|
|
}
|
|
}
|
|
self.idle_cycle();
|
|
} else {
|
|
let mut first = true;
|
|
let mut access = NonSeq;
|
|
for r in 0..16 {
|
|
if rlist.bit(r) {
|
|
let val = if r != base_reg {
|
|
if r == REG_PC {
|
|
self.pc_arm() + 12
|
|
} else {
|
|
self.get_reg(r)
|
|
}
|
|
} else {
|
|
if first {
|
|
old_base
|
|
} else {
|
|
let x = rlist_count * 4;
|
|
if ascending {
|
|
old_base + x
|
|
} else {
|
|
old_base - x
|
|
}
|
|
}
|
|
};
|
|
|
|
if full {
|
|
addr = addr.wrapping_add(4);
|
|
}
|
|
|
|
first = false;
|
|
|
|
self.store_aligned_32(addr, val, access);
|
|
access = Seq;
|
|
if !full {
|
|
addr = addr.wrapping_add(4);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
} else {
|
|
if is_load {
|
|
let val = self.ldr_word(addr, NonSeq);
|
|
self.set_reg(REG_PC, val & !3);
|
|
self.reload_pipeline32();
|
|
result = CpuAction::PipelineFlushed;
|
|
} else {
|
|
// block data store with empty rlist
|
|
let addr = match (ascending, full) {
|
|
(false, false) => addr.wrapping_sub(0x3c),
|
|
(false, true) => addr.wrapping_sub(0x40),
|
|
(true, false) => addr,
|
|
(true, true) => addr.wrapping_add(4),
|
|
};
|
|
self.store_aligned_32(addr, self.pc + 4, NonSeq);
|
|
}
|
|
addr = if ascending {
|
|
addr.wrapping_add(0x40)
|
|
} else {
|
|
addr.wrapping_sub(0x40)
|
|
};
|
|
}
|
|
|
|
if user_bank_transfer {
|
|
self.change_mode(self.cpsr.mode(), old_mode);
|
|
}
|
|
|
|
if writeback {
|
|
self.set_reg(base_reg, addr as u32);
|
|
}
|
|
|
|
result
|
|
}
|
|
|
|
/// Multiply and Multiply-Accumulate (MUL, MLA)
|
|
/// Execution Time: 1S+mI for MUL, and 1S+(m+1)I for MLA.
|
|
pub fn exec_arm_mul_mla(&mut self, insn: u32) -> CpuAction {
|
|
let rd = insn.bit_range(16..20) as usize;
|
|
let rn = insn.bit_range(12..16) as usize;
|
|
let rs = insn.rs();
|
|
let rm = insn.rm();
|
|
|
|
// // check validity
|
|
// assert!(!(REG_PC == rd || REG_PC == rn || REG_PC == rs || REG_PC == rm));
|
|
// assert!(rd != rm);
|
|
|
|
let op1 = self.get_reg(rm);
|
|
let op2 = self.get_reg(rs);
|
|
let mut result = op1.wrapping_mul(op2);
|
|
|
|
if insn.accumulate_flag() {
|
|
result = result.wrapping_add(self.get_reg(rn));
|
|
self.idle_cycle();
|
|
}
|
|
|
|
self.set_reg(rd, result);
|
|
|
|
let m = self.get_required_multipiler_array_cycles(op2);
|
|
for _ in 0..m {
|
|
self.idle_cycle();
|
|
}
|
|
|
|
if insn.set_cond_flag() {
|
|
self.cpsr.set_N((result as i32) < 0);
|
|
self.cpsr.set_Z(result == 0);
|
|
self.cpsr.set_C(false);
|
|
self.cpsr.set_V(false);
|
|
}
|
|
|
|
CpuAction::AdvancePC(Seq)
|
|
}
|
|
|
|
/// Multiply Long and Multiply-Accumulate Long (MULL, MLAL)
|
|
/// Execution Time: 1S+(m+1)I for MULL, and 1S+(m+2)I for MLAL
|
|
pub fn exec_arm_mull_mlal(&mut self, insn: u32) -> CpuAction {
|
|
let rd_hi = insn.rd_hi();
|
|
let rd_lo = insn.rd_lo();
|
|
let rs = insn.rs();
|
|
let rm = insn.rm();
|
|
|
|
let op1 = self.get_reg(rm);
|
|
let op2 = self.get_reg(rs);
|
|
let mut result: u64 = if insn.u_flag() {
|
|
// signed
|
|
(op1 as i32 as i64).wrapping_mul(op2 as i32 as i64) as u64
|
|
} else {
|
|
(op1 as u64).wrapping_mul(op2 as u64)
|
|
};
|
|
if insn.accumulate_flag() {
|
|
let hi = self.get_reg(rd_hi) as u64;
|
|
let lo = self.get_reg(rd_lo) as u64;
|
|
result = result.wrapping_add(hi << 32 | lo);
|
|
self.idle_cycle();
|
|
}
|
|
self.set_reg(rd_hi, (result >> 32) as i32 as u32);
|
|
self.set_reg(rd_lo, (result & 0xffffffff) as i32 as u32);
|
|
self.idle_cycle();
|
|
let m = self.get_required_multipiler_array_cycles(self.get_reg(rs));
|
|
for _ in 0..m {
|
|
self.idle_cycle();
|
|
}
|
|
|
|
if insn.set_cond_flag() {
|
|
self.cpsr.set_N(result.bit(63));
|
|
self.cpsr.set_Z(result == 0);
|
|
self.cpsr.set_C(false);
|
|
self.cpsr.set_V(false);
|
|
}
|
|
|
|
CpuAction::AdvancePC(Seq)
|
|
}
|
|
|
|
/// ARM Opcodes: Memory: Single Data Swap (SWP)
|
|
/// Execution Time: 1S+2N+1I. That is, 2N data cycles, 1S code cycle, plus 1I.
|
|
pub fn exec_arm_swp(&mut self, insn: u32) -> CpuAction {
|
|
let base_addr = self.get_reg(insn.bit_range(16..20) as usize);
|
|
let rd = insn.bit_range(12..16) as usize;
|
|
if insn.transfer_size() == 1 {
|
|
let t = self.load_8(base_addr, NonSeq);
|
|
self.store_8(base_addr, self.get_reg(insn.rm()) as u8, Seq);
|
|
self.set_reg(rd, t as u32);
|
|
} else {
|
|
let t = self.ldr_word(base_addr, NonSeq);
|
|
self.store_aligned_32(base_addr, self.get_reg(insn.rm()), Seq);
|
|
self.set_reg(rd, t as u32);
|
|
}
|
|
self.idle_cycle();
|
|
|
|
CpuAction::AdvancePC(NonSeq)
|
|
}
|
|
|
|
/// ARM Software Interrupt
|
|
/// Execution Time: 2S+1N
|
|
pub fn exec_arm_swi(&mut self, insn: u32) -> CpuAction {
|
|
self.software_interrupt(self.pc - 4, insn.swi_comment()); // Implies 2S + 1N
|
|
CpuAction::PipelineFlushed
|
|
}
|
|
}
|