This repository has been archived on 2024-12-14. You can view files and clone it, but cannot push or open issues or pull requests.
rustboyadvance-ng/src/core/arm7tdmi/bus.rs
Michel Heily d86cc87c79 Add WAITCNT, and refactor cycle calculation
Former-commit-id: e1ee5c9ce1f1db549fddd80907467da51e63b676
2019-08-07 09:50:33 +03:00

18 lines
512 B
Rust

use super::Addr;
pub trait Bus {
fn read_32(&self, addr: Addr) -> u32;
fn read_16(&self, addr: Addr) -> u16;
fn read_8(&self, addr: Addr) -> u8;
fn write_32(&mut self, addr: Addr, value: u32);
fn write_16(&mut self, addr: Addr, value: u16);
fn write_8(&mut self, addr: Addr, value: u8);
fn get_bytes(&self, range: std::ops::Range<u32>) -> Vec<u8> {
let mut bytes = Vec::new();
for b in range {
bytes.push(self.read_8(b));
}
bytes
}
}