
- Add tracing of opcodes and potentially more stuff - Add option to run a script file at the beginnig (I use it to redirect traces to a file) - Support breakpoints again Former-commit-id: 4e988d6bc1a59456c96547f0320a6d9abedcae00
498 lines
15 KiB
Rust
498 lines
15 KiB
Rust
use std::fmt;
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use ansi_term::{Colour, Style};
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pub use super::exception::Exception;
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use super::{
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arm::*, bus::Bus, psr::RegPSR, reg_string, thumb::ThumbInstruction, Addr, CpuMode, CpuResult,
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CpuState, DecodedInstruction, InstructionDecoder,
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};
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use super::super::sysbus::{
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MemoryAccess, MemoryAccessType, MemoryAccessType::*, MemoryAccessWidth::*, SysBus,
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};
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#[derive(Debug, PartialEq)]
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enum PipelineState {
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Refill1,
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Refill2,
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Execute,
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}
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impl Default for PipelineState {
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fn default() -> PipelineState {
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PipelineState::Refill1
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}
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}
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#[derive(Debug, Default)]
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pub struct Core {
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pub pc: u32,
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pub gpr: [u32; 15],
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// r13 and r14 are banked for all modes. System&User mode share them
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pub(super) gpr_banked_r13: [u32; 6],
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pub(super) gpr_banked_r14: [u32; 6],
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// r8-r12 are banked for fiq mode
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pub(super) gpr_banked_old_r8_12: [u32; 5],
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pub(super) gpr_banked_fiq_r8_12: [u32; 5],
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pub cpsr: RegPSR,
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pub(super) spsr: RegPSR,
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pub(super) spsr_bank: [RegPSR; 6],
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pub(super) bs_carry_out: bool,
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pipeline_state: PipelineState,
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pipeline: [u32; 2],
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fetched_arm: u32,
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decoded_arm: u32,
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fetched_thumb: u16,
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decoded_thumb: u16,
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pub last_executed: Option<DecodedInstruction>,
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pub cycles: usize,
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// store the gpr before executing an instruction to show diff in the Display impl
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gpr_previous: [u32; 15],
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memreq: Addr,
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pub breakpoints: Vec<u32>,
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pub verbose: bool,
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}
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pub type CpuExecResult = CpuResult<()>;
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impl Core {
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pub fn new() -> Core {
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let mut cpsr = RegPSR::new(0x0000_00D3);
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Core {
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memreq: 0xffff_0000, // set memreq to an invalid addr so the first load cycle will be non-sequential
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cpsr: cpsr,
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..Default::default()
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}
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}
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pub fn set_verbose(&mut self, v: bool) {
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self.verbose = v;
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}
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pub fn get_reg(&self, r: usize) -> u32 {
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match r {
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0..=14 => self.gpr[r],
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15 => self.pc,
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_ => panic!("invalid register {}", r),
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}
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}
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pub fn get_reg_user(&mut self, r: usize) -> u32 {
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match r {
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0..=7 => self.gpr[r],
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8..=12 => {
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if self.cpsr.mode() == CpuMode::Fiq {
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self.gpr[r]
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} else {
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self.gpr_banked_old_r8_12[r - 8]
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}
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}
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13 => self.gpr_banked_r13[0],
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14 => self.gpr_banked_r14[0],
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_ => panic!("invalid register"),
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}
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}
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pub fn set_reg(&mut self, r: usize, val: u32) {
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match r {
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0...14 => self.gpr[r] = val,
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15 => self.pc = val & !1,
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_ => panic!("invalid register"),
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}
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}
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pub fn set_reg_user(&mut self, r: usize, val: u32) {
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match r {
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0..=7 => self.gpr[r] = val,
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8..=12 => {
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if self.cpsr.mode() == CpuMode::Fiq {
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self.gpr[r] = val;
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} else {
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self.gpr_banked_old_r8_12[r - 8] = val;
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}
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}
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13 => {
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self.gpr_banked_r13[0] = val;
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}
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14 => {
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self.gpr_banked_r14[0] = val;
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}
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_ => panic!("invalid register"),
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}
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}
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pub(super) fn write_32(&mut self, addr: Addr, value: u32, bus: &mut SysBus) {
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bus.write_32(addr & !0x3, value);
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}
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pub(super) fn write_16(&mut self, addr: Addr, value: u16, bus: &mut SysBus) {
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bus.write_16(addr & !0x1, value);
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}
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pub(super) fn write_8(&mut self, addr: Addr, value: u8, bus: &mut SysBus) {
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bus.write_8(addr, value);
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}
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/// Helper function for "ldr" instruction that handles misaligned addresses
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pub(super) fn ldr_word(&mut self, addr: Addr, bus: &SysBus) -> u32 {
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if addr & 0x3 != 0 {
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let rotation = (addr & 0x3) << 3;
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let value = bus.read_32(addr & !0x3);
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self.ror(value, rotation, self.cpsr.C(), false, false)
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} else {
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bus.read_32(addr)
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}
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}
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/// Helper function for "ldrh" instruction that handles misaligned addresses
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pub(super) fn ldr_half(&mut self, addr: Addr, bus: &SysBus) -> u32 {
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if addr & 0x1 != 0 {
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let rotation = (addr & 0x1) << 3;
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let value = bus.read_16(addr & !0x1);
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self.ror(value as u32, rotation, self.cpsr.C(), false, false)
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} else {
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bus.read_16(addr) as u32
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}
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}
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/// Helper function for "ldrsh" instruction that handles misaligned addresses
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pub(super) fn ldr_sign_half(&mut self, addr: Addr, bus: &SysBus) -> u32 {
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if addr & 0x1 != 0 {
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bus.read_8(addr) as i8 as i32 as u32
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} else {
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bus.read_16(addr) as i16 as i32 as u32
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}
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}
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pub fn get_registers(&self) -> [u32; 15] {
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self.gpr.clone()
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}
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pub(super) fn change_mode(&mut self, old_mode: CpuMode, new_mode: CpuMode) {
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let new_index = new_mode.bank_index();
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let old_index = old_mode.bank_index();
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if new_index == old_index {
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return;
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}
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self.spsr_bank[old_index] = self.spsr;
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self.gpr_banked_r13[old_index] = self.gpr[13];
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self.gpr_banked_r14[old_index] = self.gpr[14];
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self.spsr = self.spsr_bank[new_index];
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self.gpr[13] = self.gpr_banked_r13[new_index];
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self.gpr[14] = self.gpr_banked_r14[new_index];
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if new_mode == CpuMode::Fiq {
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for r in 0..5 {
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self.gpr_banked_old_r8_12[r] = self.gpr[r + 8];
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self.gpr[r + 8] = self.gpr_banked_fiq_r8_12[r];
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}
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} else if old_mode == CpuMode::Fiq {
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for r in 0..5 {
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self.gpr_banked_fiq_r8_12[r] = self.gpr[r + 8];
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self.gpr[r + 8] = self.gpr_banked_old_r8_12[r];
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}
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}
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self.cpsr.set_mode(new_mode);
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}
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/// Resets the cpu
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pub fn reset(&mut self, sb: &mut SysBus) {
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self.exception(sb, Exception::Reset, 0);
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}
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pub fn word_size(&self) -> usize {
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match self.cpsr.state() {
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CpuState::ARM => 4,
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CpuState::THUMB => 2,
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}
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}
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pub fn cycles(&self) -> usize {
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self.cycles
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}
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pub(super) fn add_cycle(&mut self) {
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// println!("<cycle I-Cyclel> total: {}", self.cycles);
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self.cycles += 1;
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}
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pub(super) fn add_cycles(&mut self, addr: Addr, bus: &SysBus, access: MemoryAccess) {
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let cycles_to_add = 1 + bus.get_cycles(addr, access);
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// println!("<cycle {:#x} {}> took: {}", addr, access, cycles_to_add);
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self.cycles += cycles_to_add;
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}
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pub(super) fn cycle_type(&self, addr: Addr) -> MemoryAccessType {
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if addr == self.memreq || addr == self.memreq.wrapping_add(self.word_size() as Addr) {
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Seq
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} else {
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NonSeq
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}
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}
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pub(super) fn get_required_multipiler_array_cycles(&self, rs: u32) -> usize {
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if rs & 0xff == rs {
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1
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} else if rs & 0xffff == rs {
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2
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} else if rs & 0xffffff == rs {
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3
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} else {
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4
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}
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}
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#[allow(non_snake_case)]
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pub(super) fn S_cycle32(&mut self, sb: &SysBus, addr: u32) {
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self.cycles += 1;
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self.cycles += sb.get_cycles(addr, Seq + MemoryAccess32);
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}
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#[allow(non_snake_case)]
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pub(super) fn S_cycle16(&mut self, sb: &SysBus, addr: u32) {
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self.cycles += 1;
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self.cycles += sb.get_cycles(addr, Seq + MemoryAccess16);
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}
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#[allow(non_snake_case)]
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pub(super) fn S_cycle8(&mut self, sb: &SysBus, addr: u32) {
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self.cycles += 1;
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self.cycles += sb.get_cycles(addr, Seq + MemoryAccess8);
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}
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#[allow(non_snake_case)]
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pub(super) fn N_cycle32(&mut self, sb: &SysBus, addr: u32) {
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self.cycles += 1;
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self.cycles += sb.get_cycles(addr, NonSeq + MemoryAccess32);
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}
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#[allow(non_snake_case)]
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pub(super) fn N_cycle16(&mut self, sb: &SysBus, addr: u32) {
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self.cycles += 1;
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self.cycles += sb.get_cycles(addr, NonSeq + MemoryAccess16);
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}
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#[allow(non_snake_case)]
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pub(super) fn N_cycle8(&mut self, sb: &SysBus, addr: u32) {
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self.cycles += 1;
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self.cycles += sb.get_cycles(addr, NonSeq + MemoryAccess8);
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}
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pub(super) fn check_arm_cond(&self, cond: ArmCond) -> bool {
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use ArmCond::*;
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match cond {
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EQ => self.cpsr.Z(),
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NE => !self.cpsr.Z(),
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HS => self.cpsr.C(),
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LO => !self.cpsr.C(),
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MI => self.cpsr.N(),
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PL => !self.cpsr.N(),
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VS => self.cpsr.V(),
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VC => !self.cpsr.V(),
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HI => self.cpsr.C() && !self.cpsr.Z(),
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LS => !self.cpsr.C() || self.cpsr.Z(),
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GE => self.cpsr.N() == self.cpsr.V(),
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LT => self.cpsr.N() != self.cpsr.V(),
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GT => !self.cpsr.Z() && (self.cpsr.N() == self.cpsr.V()),
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LE => self.cpsr.Z() || (self.cpsr.N() != self.cpsr.V()),
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AL => true,
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}
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}
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pub(super) fn did_pipeline_flush(&self) -> bool {
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self.pipeline_state == PipelineState::Refill1
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}
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fn step_arm_exec(&mut self, insn: u32, sb: &mut SysBus) -> CpuResult<()> {
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let pc = self.pc;
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match self.pipeline_state {
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PipelineState::Refill1 => {
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self.pc = pc.wrapping_add(4);
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self.pipeline_state = PipelineState::Refill2;
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self.last_executed = None;
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}
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PipelineState::Refill2 => {
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self.pc = pc.wrapping_add(4);
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self.pipeline_state = PipelineState::Execute;
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self.last_executed = None;
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}
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PipelineState::Execute => {
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let decoded_arm = ArmInstruction::decode(insn, self.pc.wrapping_sub(8))?;
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self.gpr_previous = self.get_registers();
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self.exec_arm(sb, decoded_arm)?;
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if !self.did_pipeline_flush() {
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self.pc = pc.wrapping_add(4);
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}
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self.last_executed = Some(DecodedInstruction::Arm(decoded_arm));
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}
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}
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Ok(())
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}
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fn step_thumb_exec(&mut self, insn: u16, sb: &mut SysBus) -> CpuResult<()> {
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let pc = self.pc;
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match self.pipeline_state {
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PipelineState::Refill1 => {
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self.pc = pc.wrapping_add(2);
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self.pipeline_state = PipelineState::Refill2;
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self.last_executed = None;
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}
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PipelineState::Refill2 => {
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self.pc = pc.wrapping_add(2);
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self.pipeline_state = PipelineState::Execute;
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self.last_executed = None;
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}
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PipelineState::Execute => {
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let insn = ThumbInstruction::decode(insn, self.pc.wrapping_sub(4))?;
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self.gpr_previous = self.get_registers();
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self.exec_thumb(sb, insn)?;
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if !self.did_pipeline_flush() {
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self.pc = pc.wrapping_add(2);
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}
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self.last_executed = Some(DecodedInstruction::Thumb(insn));
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}
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}
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Ok(())
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}
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pub(super) fn flush_pipeline(&mut self, sb: &mut SysBus) {
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self.pipeline_state = PipelineState::Refill1;
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match self.cpsr.state() {
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CpuState::ARM => {
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self.N_cycle32(sb, self.pc);
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self.S_cycle32(sb, self.pc + 4);
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}
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CpuState::THUMB => {
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self.N_cycle16(sb, self.pc);
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self.S_cycle16(sb, self.pc + 2);
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}
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}
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}
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fn trace_opcode(&self, insn: u32) {
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if self.trace_opcodes && self.pipeline_state == PipelineState::Execute {
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print!("[{:08X}] PC=0x{:08x} | ", insn, self.pc);
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for r in 0..15 {
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print!("R{}=0x{:08x} ", r, self.gpr[r]);
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}
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print!(
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" N={} Z={} C={} V={} T={}\n",
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self.cpsr.N() as u8,
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self.cpsr.Z() as u8,
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self.cpsr.C() as u8,
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self.cpsr.V() as u8,
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self.cpsr.state() as u8,
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);
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}
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}
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/// Perform a pipeline step
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/// If an instruction was executed in this step, return it.
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pub fn step(&mut self, bus: &mut SysBus) -> CpuResult<()> {
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let pc = self.pc;
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let fetched_now = match self.cpsr.state() {
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CpuState::ARM => bus.read_32(pc),
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CpuState::THUMB => bus.read_16(pc) as u32,
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};
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let insn = self.pipeline[0];
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self.pipeline[0] = self.pipeline[1];
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self.pipeline[1] = fetched_now;
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match self.cpsr.state() {
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CpuState::ARM => self.step_arm_exec(insn, bus),
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CpuState::THUMB => self.step_thumb_exec(insn as u16, bus),
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}
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}
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/// Get's the address of the next instruction that is going to be executed
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pub fn get_next_pc(&self) -> Addr {
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let insn_size = self.word_size() as u32;
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match self.pipeline_state {
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PipelineState::Refill1 => self.pc,
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PipelineState::Refill2 => self.pc - insn_size,
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PipelineState::Execute => self.pc - 2 * insn_size,
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}
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}
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/// A step that returns only once an instruction was executed.
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/// Returns the address of PC before executing an instruction,
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/// and the address of the next instruction to be executed;
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pub fn step_one(&mut self, bus: &mut SysBus) -> CpuResult<DecodedInstruction> {
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loop {
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match self.pipeline_state {
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PipelineState::Execute => {
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self.step(bus)?;
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return Ok(self.last_executed.unwrap());
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}
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_ => {
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self.step(bus)?;
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}
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}
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}
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}
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pub fn get_cpu_state(&self) -> CpuState {
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self.cpsr.state()
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}
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pub fn skip_bios(&mut self) {
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self.gpr_banked_r13[0] = 0x0300_7f00; // USR/SYS
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self.gpr_banked_r13[1] = 0x0300_7f00; // FIQ
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self.gpr_banked_r13[2] = 0x0300_7fa0; // IRQ
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self.gpr_banked_r13[3] = 0x0300_7fe0; // SVC
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self.gpr_banked_r13[4] = 0x0300_7f00; // ABT
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self.gpr_banked_r13[5] = 0x0300_7f00; // UND
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self.gpr[13] = 0x0300_7f00;
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self.gpr[14] = 0x0800_0000;
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self.pc = 0x0800_0000;
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self.cpsr.set(0x5f);
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}
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}
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impl fmt::Display for Core {
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fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
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writeln!(f, "ARM7TDMI Core Status:")?;
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writeln!(f, "\tCycles: {}", self.cycles)?;
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writeln!(f, "\tCPSR: {}", self.cpsr)?;
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writeln!(f, "\tGeneral Purpose Registers:")?;
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let reg_normal_style = Style::new().bold();
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let reg_dirty_style = Colour::Black.bold().on(Colour::Yellow);
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let gpr = self.get_registers();
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for i in 0..15 {
|
|
let mut reg_name = reg_string(i).to_string();
|
|
reg_name.make_ascii_uppercase();
|
|
|
|
let style = if gpr[i] != self.gpr_previous[i] {
|
|
®_dirty_style
|
|
} else {
|
|
®_normal_style
|
|
};
|
|
|
|
let entry = format!("\t{:-3} = 0x{:08x}", reg_name, gpr[i]);
|
|
|
|
write!(
|
|
f,
|
|
"{}{}",
|
|
style.paint(entry),
|
|
if (i + 1) % 4 == 0 { "\n" } else { "" }
|
|
)?;
|
|
}
|
|
let pc = format!("\tPC = 0x{:08x}", self.get_next_pc());
|
|
writeln!(f, "{}", reg_normal_style.paint(pc))
|
|
}
|
|
}
|