Commit graph

13 commits

Author SHA1 Message Date
Michel Heily
b288625b9a Improve the debugger
- Add tracing of opcodes and potentially more stuff
- Add option to run a script file at the beginnig (I use it to redirect
traces to a file)
- Support breakpoints again


Former-commit-id: 4e988d6bc1a59456c96547f0320a6d9abedcae00
2019-11-16 18:17:53 +02:00
Michel Heily
7e98af80c2 Fixes to ALU, passing mGBA carry tests
Former-commit-id: 14a4293b2511c7c63a920e6344e89b209ca7c5ee
2019-11-16 18:17:53 +02:00
Michel Heily
1d088accb8 mGBA test suite now boots!
Fix tons of bug and reimplemented some of the core code.
Add a neat feature for debug builds:
When the cpu "swi 0x55" instruction, a breakpoint is triggered on the
host.


Former-commit-id: 959249df4374327d90b2503d7a45f8d5d27995a6
2019-11-12 18:22:00 +02:00
Michel Heily
c117cbe924 Make the debugger work again, but currently breakpoints are not supported.
Added memory write command and the ability to pause the debugger with Ctrl-C


Former-commit-id: 83d141fa191dadefb84f7c9de163631a69af8324
2019-11-12 18:22:00 +02:00
Michel Heily
3a1d5c10ce Fix many bugs, refactor many things..
Passing: Armwrestler, cpu_test by Dead_Body

Former-commit-id: 80d815d110c5341515dd01c476a0d7e25ecb66a8
2019-11-09 01:06:24 +02:00
Michel Heily
acd0e4f338 cpu: Refactor instructions to use explicit cycle counting.
The way cycles were counted up untill now was not accurate enough,
I've avoided doing so because the instruction implementation looks
bloated this way, but I've had problems with cycle accuracy with tonc's
timer demo.

This is not entirely correct though, and I'm 100% sure there are some
mistakes, but works good enough for now.


Former-commit-id: 748faaf99fe2f42925c0a2110192c6a01e5d27d4
2019-08-08 20:05:09 +03:00
Michel Heily
c7dd713605 The big ioregs refactoring.
This commit refactors the ioregs:
* Use bitfield crate to implement the GPU ioregs.
* IoRegs are stored in their own variables bindings (i.e, Gpu related ioregs are now fields of the Gpu struct)
  - This optimize performance quiet alot from my testings - since every scanline was accessing deseralizing ioregs from sysbus. (Getting constant 59fps now)
* For now, comment out DMA model

Also, cleaned the code up to eliminate rustc warnings.


Former-commit-id: 9077695c446ebd1a71783acfdd9819245aa02d7a
2019-08-03 00:24:15 +03:00
Michel Heily
1b5626a1a7 armwrestler-fix: Refactor barrel shifter and fix ALU carry flag, hopefully for good.
Passing most of armwrestler ALU tests (still have bugs in UMULL and
SMULL)


Former-commit-id: 3c57ca9b5360b5c9bba74b00a5bede5a8cc496af
2019-07-26 17:55:50 +03:00
Michel Heily
009e46f6d5 armwrestler-fix: Properly handle misaligned addresses LDR/LDRH/LDRSH
Former-commit-id: 742a7c2b8413fa9d45df1575a0b14b8d1ab697c4
2019-07-22 20:25:40 +03:00
Michel Heily
2fb6f3c884 Implement (psr / usr bank) transfers for LDM_STM
Former-commit-id: 140e6a6c75f65f08f645b1a0ff2ca7c065438ce4
2019-07-22 09:21:49 +03:00
Michel Heily
c0d437b1a1 Fix exceptions and dataprocess mode change
Former-commit-id: 5892131496904b621398212b9dfc077242fa9557
2019-07-22 01:16:48 +03:00
Michel Heily
7501adfd12 Implement thumb17 (Swi)
Former-commit-id: 62d7e14e9b84e74d9236e1f0a5e961ae805f861c
2019-07-22 01:15:58 +03:00
Michel Heily
53115a9a58 Refactor core functionality into a separate module
Former-commit-id: 5d55b9eb0b63ed7c61465b4e814782165caa5002
2019-07-20 16:46:00 +03:00
Renamed from src/arm7tdmi/cpu.rs (Browse further)