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Michel Heily fb0d3acb14 Impl Thumb Format 1 untested ... Former-commit-id: e80617fd415ba951310a42c79b6ca37251d0e250		2019-07-05 14:09:04 +03:00
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arm	Impl Thumb Format 1 untested	2019-07-05 14:09:04 +03:00
thumb	Impl Thumb Format 1 untested	2019-07-05 14:09:04 +03:00
bus.rs	Move cycle counting to CPU Core	2019-07-05 13:08:07 +03:00
cpu.rs	Impl thumb Format4	2019-07-05 13:58:26 +03:00
exception.rs	Correct F flag behaviour when entrying an exception.	2019-06-29 23:01:23 +03:00
mod.rs	Implement thumb format3 instruction and add a test for it.	2019-07-03 01:26:48 +03:00
psr.rs	arm: Implement MSR_REG and fix some prefetching errors	2019-07-02 16:53:29 +03:00