armwrestler-fix: Fix writeback for LDR where rd==rn
Instead of returning an Err, the writeback should just be disabled. Former-commit-id: 91636a4eeaf76d0dbd11d250202671fcf8aaa4e6
This commit is contained in:
parent
009e46f6d5
commit
24483456ed
|
@ -208,9 +208,8 @@ impl Core {
|
||||||
/// For LDR, add y=1S+1N if Rd=R15.
|
/// For LDR, add y=1S+1N if Rd=R15.
|
||||||
fn exec_ldr_str(&mut self, bus: &mut Bus, insn: ArmInstruction) -> CpuExecResult {
|
fn exec_ldr_str(&mut self, bus: &mut Bus, insn: ArmInstruction) -> CpuExecResult {
|
||||||
let mut writeback = insn.write_back_flag();
|
let mut writeback = insn.write_back_flag();
|
||||||
|
|
||||||
if writeback && insn.rd() == insn.rn() {
|
if writeback && insn.rd() == insn.rn() {
|
||||||
return Err(CpuError::IllegalInstruction);
|
writeback = false;
|
||||||
}
|
}
|
||||||
|
|
||||||
let mut addr = self.get_reg(insn.rn());
|
let mut addr = self.get_reg(insn.rn());
|
||||||
|
@ -266,7 +265,7 @@ impl Core {
|
||||||
fn exec_ldr_str_hs(&mut self, bus: &mut Bus, insn: ArmInstruction) -> CpuExecResult {
|
fn exec_ldr_str_hs(&mut self, bus: &mut Bus, insn: ArmInstruction) -> CpuExecResult {
|
||||||
let mut writeback = insn.write_back_flag();
|
let mut writeback = insn.write_back_flag();
|
||||||
if writeback && insn.rd() == insn.rn() {
|
if writeback && insn.rd() == insn.rn() {
|
||||||
return Err(CpuError::IllegalInstruction);
|
writeback = false;
|
||||||
}
|
}
|
||||||
|
|
||||||
let mut addr = self.get_reg(insn.rn());
|
let mut addr = self.get_reg(insn.rn());
|
||||||
|
|
Reference in a new issue