ptimize: CPU Pipeline optimization part 3
Move reload_pipeline calls inside instructions. This commit yeilds yet another 5% performance improvment. The next step is to move `advance_pc` into the instructions themselves and save the `match result` per executed instruction Former-commit-id: 42193ffc48fda9943665e6a74e873186627a0b4a
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6beec306c2
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@ -45,6 +45,7 @@ impl Core {
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self.pc = (self.pc as i32).wrapping_add(insn.branch_offset()) as u32 & !1;
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self.reload_pipeline32(sb);
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CpuAction::FlushPipeline
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}
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@ -56,13 +57,15 @@ impl Core {
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if addr.bit(0) {
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addr = addr & !0x1;
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self.cpsr.set_state(CpuState::THUMB);
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self.pc = addr;
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self.reload_pipeline16(sb);
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} else {
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addr = addr & !0x3;
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self.cpsr.set_state(CpuState::ARM);
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self.pc = addr;
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self.reload_pipeline32(sb);
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}
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self.pc = addr;
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CpuAction::FlushPipeline
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}
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@ -250,6 +253,11 @@ impl Core {
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if let Some(alu_res) = alu_res {
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self.set_reg(reg_rd, alu_res as u32);
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if reg_rd == REG_PC {
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// T bit might have changed
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match self.cpsr.state() {
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CpuState::ARM => self.reload_pipeline32(sb),
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CpuState::THUMB => self.reload_pipeline16(sb),
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};
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result = CpuAction::FlushPipeline;
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}
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}
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@ -307,6 +315,7 @@ impl Core {
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self.add_cycle();
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if dest_reg == REG_PC {
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self.reload_pipeline32(sb);
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result = CpuAction::FlushPipeline;
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}
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} else {
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@ -391,6 +400,7 @@ impl Core {
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self.add_cycle();
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if dest_reg == REG_PC {
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self.reload_pipeline32(sb);
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result = CpuAction::FlushPipeline;
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}
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} else {
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@ -497,6 +507,7 @@ impl Core {
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if psr_transfer {
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self.transfer_spsr_mode();
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}
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self.reload_pipeline32(sb);
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result = CpuAction::FlushPipeline;
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}
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@ -551,6 +562,7 @@ impl Core {
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if is_load {
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let val = self.ldr_word(addr, sb);
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self.set_reg(REG_PC, val & !3);
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self.reload_pipeline32(sb);
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result = CpuAction::FlushPipeline;
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} else {
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self.write_32(addr, self.pc + 4, sb);
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@ -320,7 +320,7 @@ impl Core {
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let result = self.exec_arm(sb, decoded_arm);
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match result {
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CpuAction::AdvancePC => self.advance_arm(),
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CpuAction::FlushPipeline => self.reload_pipeline(sb),
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CpuAction::FlushPipeline => {},
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}
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}
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@ -334,7 +334,7 @@ impl Core {
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let result = self.exec_thumb(sb, decoded_thumb);
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match result {
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CpuAction::AdvancePC => self.advance_thumb(),
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CpuAction::FlushPipeline => self.reload_pipeline(sb),
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CpuAction::FlushPipeline => {},
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}
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}
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@ -56,13 +56,13 @@ impl Core {
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// Set PC to vector address
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self.pc = e as u32;
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self.reload_pipeline32(sb);
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}
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pub fn irq(&mut self, sb: &mut SysBus) {
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if !self.cpsr.irq_disabled() {
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let lr = self.get_next_pc() + 4;
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self.exception(sb, Exception::Irq, lr);
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self.reload_pipeline32(sb);
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}
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}
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@ -177,7 +177,8 @@ impl Core {
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OpFormat5::ADD => {
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self.set_reg(dst_reg, op1.wrapping_add(op2));
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if dst_reg == REG_PC {
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result = CpuAction::FlushPipeline
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result = CpuAction::FlushPipeline;
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self.reload_pipeline16(sb);
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}
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}
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OpFormat5::CMP => {
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@ -190,6 +191,7 @@ impl Core {
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self.set_reg(dst_reg, op2 as u32);
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if dst_reg == REG_PC {
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result = CpuAction::FlushPipeline;
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self.reload_pipeline16(sb);
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}
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}
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}
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@ -421,6 +423,7 @@ impl Core {
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pop(self, sb, REG_PC);
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self.pc = self.pc & !1;
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result = CpuAction::FlushPipeline;
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self.reload_pipeline16(sb);
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}
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self.S_cycle16(sb, self.pc + 2);
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} else {
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@ -508,6 +511,7 @@ impl Core {
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let val = sb.read_32(addr);
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self.set_reg(REG_PC, val & !1);
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result = CpuAction::FlushPipeline;
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self.reload_pipeline16(sb);
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} else {
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sb.write_32(addr, self.pc + 2);
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}
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@ -531,6 +535,7 @@ impl Core {
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let offset = insn.bcond_offset();
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self.S_cycle16(sb, self.pc);
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self.pc = (self.pc as i32).wrapping_add(offset) as u32;
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self.reload_pipeline16(sb);
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CpuAction::FlushPipeline
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}
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}
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@ -539,7 +544,6 @@ impl Core {
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fn exec_thumb_swi(&mut self, sb: &mut SysBus, _insn: ThumbInstruction) -> CpuAction {
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self.N_cycle16(sb, self.pc);
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self.exception(sb, Exception::SoftwareInterrupt, self.pc - 2);
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CpuAction::FlushPipeline
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}
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@ -548,7 +552,7 @@ impl Core {
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let offset = ((insn.offset11() << 21) >> 20) as i32;
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self.pc = (self.pc as i32).wrapping_add(offset) as u32;
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self.S_cycle16(sb, self.pc);
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self.reload_pipeline16(sb);
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CpuAction::FlushPipeline
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}
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@ -565,7 +569,7 @@ impl Core {
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let next_pc = (self.pc - 2) | 1;
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self.pc = ((self.gpr[REG_LR] & !1) as i32).wrapping_add(off) as u32;
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self.gpr[REG_LR] = next_pc;
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self.reload_pipeline16(sb);
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CpuAction::FlushPipeline
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} else {
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off = (off << 21) >> 9;
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