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perf: Move pc to the beginning of the CPU struct

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Former-commit-id: 1b17095bee5c6010d3792fc220a8abcf3a373207
Former-commit-id: 5e65dad6398ef6e9d907d086c982fd70e85c9184
This commit is contained in:
Michel Heily 2021-07-02 12:44:12 +03:00 committed by MichelOS
parent 892dfbe395
commit 7e96be21ae
3 changed files with 16 additions and 10 deletions
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11
core/build.rs
View file

@ -30,10 +30,17 @@ fn thumb_decode(i: u16) -> (&'static str, String) {
} else if i & 0xe000 == 0x2000 { } else if i & 0xe000 == 0x2000 {
( (
"DataProcessImm", "DataProcessImm",
String::from("exec_thumb_data_process_imm"), format!(
"exec_thumb_data_process_imm::<{OP}, {RD}>",
OP = i.bit_range(11..13) as u8,
RD = i.bit_range(8..11)
),
) )
} else if i & 0xfc00 == 0x4000 { } else if i & 0xfc00 == 0x4000 {
("AluOps", String::from("exec_thumb_alu_ops")) (
"AluOps",
format!("exec_thumb_alu_ops::<{OP}>", OP = i.bit_range(6..10) as u16),
)
} else if i & 0xfc00 == 0x4400 { } else if i & 0xfc00 == 0x4400 {
( (
"HiRegOpOrBranchExchange", "HiRegOpOrBranchExchange",

2
core/src/arm7tdmi/cpu.rs
View file

@ -113,11 +113,11 @@ impl Default for DebuggerState {
#[derive(Clone, Debug)] #[derive(Clone, Debug)]
pub struct Core<I: MemoryInterface> { pub struct Core<I: MemoryInterface> {
pub pc: u32,
pub(super) bus: Shared<I>, pub(super) bus: Shared<I>,
next_fetch_access: MemoryAccess, next_fetch_access: MemoryAccess,
pipeline: [u32; 2], pipeline: [u32; 2],
pub pc: u32,
pub gpr: [u32; 15], pub gpr: [u32; 15],
pub cpsr: RegPSR, pub cpsr: RegPSR,

13
core/src/arm7tdmi/thumb/exec.rs
View file

@ -62,11 +62,10 @@ impl<I: MemoryInterface> Core<I> {
/// Format 3 /// Format 3
/// Execution Time: 1S /// Execution Time: 1S
pub(in super::super) fn exec_thumb_data_process_imm(&mut self, insn: u16) -> CpuAction { pub(in super::super) fn exec_thumb_data_process_imm<const OP: u8, const RD: usize>(&mut self, insn: u16) -> CpuAction {
use OpFormat3::*; use OpFormat3::*;
let op = insn.format3_op(); let op = OpFormat3::from_u8(OP).unwrap();
let rd = insn.bit_range(8..11) as usize; let op1 = self.gpr[RD];
let op1 = self.gpr[rd];
let op2_imm = (insn & 0xff) as u32; let op2_imm = (insn & 0xff) as u32;
let mut carry = self.cpsr.C(); let mut carry = self.cpsr.C();
let mut overflow = self.cpsr.V(); let mut overflow = self.cpsr.V();
@ -78,7 +77,7 @@ impl<I: MemoryInterface> Core<I> {
let arithmetic = op == ADD || op == SUB; let arithmetic = op == ADD || op == SUB;
self.alu_update_flags(result, arithmetic, carry, overflow); self.alu_update_flags(result, arithmetic, carry, overflow);
if op != CMP { if op != CMP {
self.gpr[rd] = result as u32; self.gpr[RD] = result as u32;
} }
CpuAction::AdvancePC(Seq) CpuAction::AdvancePC(Seq)
@ -89,7 +88,7 @@ impl<I: MemoryInterface> Core<I> {
/// 1S for AND,EOR,ADC,SBC,TST,NEG,CMP,CMN,ORR,BIC,MVN /// 1S for AND,EOR,ADC,SBC,TST,NEG,CMP,CMN,ORR,BIC,MVN
/// 1S+1I for LSL,LSR,ASR,ROR /// 1S+1I for LSL,LSR,ASR,ROR
/// 1S+mI for MUL on ARMv4 (m=1..4; depending on MSBs of incoming Rd value) /// 1S+mI for MUL on ARMv4 (m=1..4; depending on MSBs of incoming Rd value)
pub(in super::super) fn exec_thumb_alu_ops(&mut self, insn: u16) -> CpuAction { pub(in super::super) fn exec_thumb_alu_ops<const OP: u16>(&mut self, insn: u16) -> CpuAction {
let rd = (insn & 0b111) as usize; let rd = (insn & 0b111) as usize;
let rs = insn.rs(); let rs = insn.rs();
let dst = self.get_reg(rd); let dst = self.get_reg(rd);
@ -99,7 +98,7 @@ impl<I: MemoryInterface> Core<I> {
let mut overflow = self.cpsr.V(); let mut overflow = self.cpsr.V();
use ThumbAluOps::*; use ThumbAluOps::*;
let op = insn.format4_alu_op(); let op = ThumbAluOps::from_u16(OP).unwrap();
macro_rules! shifter_op { macro_rules! shifter_op {
($bs_op:expr) => {{ ($bs_op:expr) => {{